IRC logs for #openrisc Tuesday, 2013-02-05

_franck_LoneTech: I can't your patch is working because while I was testing my setup I found out it wasn't working as expected...10:09
_franck_breaking on jump instruction then stepi doen't work. I need to check my configuration.10:09
LoneTech_franck_: I'm not surprised that it breaks on jumps, actually. does the other patch not?10:26
LoneTech(btw, that's probably our old bane the delay slot)10:27
_franck_my configuration was supposed to work while breaking on jumps10:34
LoneTechwell, my patch is incomplete. I expected that to be a trouble area.10:36
_franck_did you try to ru openocd with the jtag_vpi interface ? then you can connect to the simulation and debug the debug thing much more easily10:37
LoneTechnot yet10:37
tgs3stekern: well as an outside newb, I was wondering,13:28
tgs3stekern: would it not be a way to have 100% open hardware13:29
tgs31) deisng 100% open source/hardware FPGA module  2) make it as affordable ASIC (super expensive - kickstater?)   3) then use this cheap per piece FPGA modules to create other opencore projects  4) join say 10x10 such modules and create big FPGA to implement reasonably priced 100% open OpenRISC cpu on it  5) do same for other parts of mainboard/SoC and have 100% absolutelly open and verifiable trusted computer13:30
stekernwhat is an "open source fpga module"?13:41
LoneTechI think he means an sram based fpga in rtl, to the degree we can order one from a fab14:39
LoneTechI guess to reach that trust though you need to uncap a few and check that the layout matches with microscopy15:01

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