| _franck_ | LoneTech: I can't your patch is working because while I was testing my setup I found out it wasn't working as expected... | 10:09 |
|---|---|---|
| _franck_ | breaking on jump instruction then stepi doen't work. I need to check my configuration. | 10:09 |
| LoneTech | _franck_: I'm not surprised that it breaks on jumps, actually. does the other patch not? | 10:26 |
| LoneTech | (btw, that's probably our old bane the delay slot) | 10:27 |
| _franck_ | my configuration was supposed to work while breaking on jumps | 10:34 |
| LoneTech | ok | 10:36 |
| LoneTech | well, my patch is incomplete. I expected that to be a trouble area. | 10:36 |
| _franck_ | did you try to ru openocd with the jtag_vpi interface ? then you can connect to the simulation and debug the debug thing much more easily | 10:37 |
| _franck_ | s/ru/run | 10:37 |
| LoneTech | not yet | 10:37 |
| tgs3 | stekern: well as an outside newb, I was wondering, | 13:28 |
| tgs3 | stekern: would it not be a way to have 100% open hardware | 13:29 |
| tgs3 | 1) deisng 100% open source/hardware FPGA module 2) make it as affordable ASIC (super expensive - kickstater?) 3) then use this cheap per piece FPGA modules to create other opencore projects 4) join say 10x10 such modules and create big FPGA to implement reasonably priced 100% open OpenRISC cpu on it 5) do same for other parts of mainboard/SoC and have 100% absolutelly open and verifiable trusted computer | 13:30 |
| stekern | what is an "open source fpga module"? | 13:41 |
| LoneTech | I think he means an sram based fpga in rtl, to the degree we can order one from a fab | 14:39 |
| LoneTech | I guess to reach that trust though you need to uncap a few and check that the layout matches with microscopy | 15:01 |
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