| stekern | woho, three more lines of console output! | 11:26 |
|---|---|---|
| stekern | i.e. initramfs unpacking passes now | 11:27 |
| stekern | juliusb: you around? | 12:00 |
| stekern | what pic option was the or1200 compliant? | 12:00 |
| stekern | nm, it's LATCHED_LEVEL | 12:19 |
| stekern | http://pastie.org/6032783 | 12:22 |
| stekern | viktory! | 12:22 |
| stekern | *victory ;) | 12:24 |
| stekern | you know you're a geek when you feel that '!Solid' is a bad name choice for a brand, because it will be interpreted as 'not solid' | 13:31 |
| stekern | (I'm still at the fashion fair in copenhagen) | 13:32 |
| _franck_ | :) | 14:31 |
| _franck_ | stekern: well done with mor1kx | 14:32 |
| stekern | _franck_: thanks | 14:46 |
| stekern | still a lot of things to do, but this is a leap forward | 14:46 |
| stekern | running limux is in itself a pretty good testbench, it brought out a couple of issues that our testsuite didn't catch | 14:47 |
| stekern | I'll look into creating tests for them, but chances are they are to complex to easily reproduce in a test | 14:49 |
| stekern | and fixing one issue makes one test in the testsuite fail, so I have to look into that too | 14:51 |
| stekern | oh, and still only works with icache disabled | 14:54 |
| stekern | will probably need to patch the kernel to work with VIPT cache | 14:55 |
| skyfex | Why is ORPSoC for this board not (easily) available? http://opencores.org/or1k/Ordb2a-ep4ce22 | 15:01 |
| stekern | hmm, actually the kernel might work as is as long as the block+set width <= 13 bits | 17:51 |
| stekern | so with a 2-way cache, max 16kb cache | 17:57 |
| juliusb | stekern: yes, a weird hybrid of level and edge-triggered interrupts | 18:10 |
| juliusb | VIPT cache? | 18:11 |
| juliusb | skyfex: not sure, on one ever properly released a port I think, but it's rolled into the VM image with development environment for that board you can download I believe | 18:12 |
| stekern | juliusb: virtually indexed, physically tagged | 18:49 |
| stekern | the icache is atm | 18:49 |
| stekern | the dcache will be in the future | 18:49 |
| stekern | we still have a 1-cycle delay on load/stores into dcache | 18:50 |
| stekern | the point is that you can do the cache lookup in parallell with the address translation | 18:57 |
| juliusb | ah right, cool | 19:41 |
Generated by irclog2html.py 2.15.2 by Marius Gedminas - find it at mg.pov.lt!