| @stekern | olofk: yup, it works pretty well iirc | 06:10 |
|---|---|---|
| @stekern | http://i6.aijaa.com/b/00569/7837382.png | 06:14 |
| @stekern | I repeat; pipeline hazards are a b*tch | 11:13 |
| @stekern | juliusb: I start to understand why you choose to cut it off at execute ;) | 11:16 |
| @stekern | in hindsight, it's performance is pretty impressive considering lsu ops are bound to be pretty slow | 11:25 |
| @stekern | they are still slow in my rework since I'm using the registered output from alu as the address, so 1 cycle extr latency | 11:37 |
| @stekern | connecting the output straight to the adder output creates that really long path out on the wb bus | 11:38 |
| @stekern | I'm thinking about connecting the exec address to the cache only, so we'll get fast cache hit accesses, but slower "cache miss" (or out of cache accesses) | 11:39 |
| @stekern | but let's make it work as it is first... | 11:41 |
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