| @juliusb | mmm, just spotted an interesting bug in some code executing | 02:12 |
|---|---|---|
| @juliusb | the flag status isn't maintained across an exception | 02:12 |
| @juliusb | that's in the software in ORPSoCv2/mor1kx-dev-env | 02:14 |
| @juliusb | hmm, making making ESR the same across exceptions fixes things | 02:21 |
| @juliusb | that's dodgy :-/ how come I've never seen that before! I'm not quire what happens, to be honest, the only thing we have is timer exceptions firing, there shouldn't be anything else changing the ESR during the handling of that | 02:23 |
| @juliusb | (by making ESR the same, I mean maintining it, ie putting it on te stack and restoring it before l.rfe'ing) | 02:25 |
| @juliusb | maybe an mor1kx pronto bug | 02:38 |
| -!- X-Scale is now known as Guest6000 | 06:06 | |
| -!- Guest6000 is now known as X-Scale | 06:09 | |
| @stekern | juliusb: without relly giving the thing alot of thought, but isn't the flag decoupled from spr_sr here? | 09:34 |
| @stekern | https://github.com/openrisc/mor1kx/blob/master/rtl/verilog/mor1kx_ctrl_prontoespresso.v#L502 | 09:34 |
| @stekern | I had a similiar bug when I moved the branches into decode stage, now I changed that to use spr_sr as the "current flag" | 09:35 |
| -!- jeremy_bennett is now known as jeremybennett | 10:18 | |
| @juliusb | jonibo: I didn't like your email man, Ruben has legitimate arguments against OpenCores but to protest this by going against something the community has chosen to do (ie. cross-post until we have a single list) then it's just disruptive to anyone signed up to the OpenCore list only | 13:08 |
| @juliusb | and we're going to ask him to stop it | 13:09 |
| @juliusb | I think that's reasonable | 13:09 |
| @juliusb | but to say he's right in what he's doing isn't constructive | 13:09 |
| @juliusb | TBH i like the openrisc.net lists because they were there first and that's also the domain the OR1K Linux stuff is on | 13:11 |
| @juliusb | it's no problem, I think, to point to a list which is @lists.openrisc.net for the OpenRISC project, but also I don't care which way it goes if we finally end up with a single list | 13:12 |
| _franck_ | olofk: I updated the patch here: http://bugzilla.opencores.org/show_bug.cgi?id=104 | 15:08 |
| _franck_ | you can apply it | 15:08 |
| @juliusb | so, looks like old diez got a bit pissed off with us arguing over the mailing lists again | 15:40 |
| @juliusb | oh well | 15:40 |
| @juliusb | but if this is us about asking him to use both lists, then too bad I guess | 15:50 |
| jeremybennett | juliusb: sometimes it has to be said. If only we could get the two lists merged, the problem would go away. | 16:12 |
| jeremybennett | The trouble is both sides agree to a merger, so long as their list is the one that remains! | 16:12 |
| _franck_ | let's create a third one :) | 16:13 |
| jeremybennett | :) | 16:13 |
| @juliusb | haha, that may almost work :P | 16:22 |
| @juliusb | closedcisc.com | 16:22 |
| @juliusb | check that website sometime later ;) | 17:09 |
| olofk | About the mailing list discussions today, I just have to say, what a fucking drama queen! | 18:23 |
| olofk | Oooo...it's too much for me. I need to take a timeout from the project | 18:24 |
| olofk | haha. I like closedcisc.com :) | 18:26 |
| olofk | Can't find any whois info on it | 18:26 |
| olofk | hmm...is a wb master required to deassert stb the cycle after it sees ack from the slave, or can it wait a couple of cycles? | 19:07 |
| @juliusb | olofk: I agree, if he can't take us complaining about him as much as he complains about us, then so be it | 19:38 |
| @juliusb | i emailed him off list asking what he meant by "doing something I asked for" | 19:39 |
| @juliusb | olofk: I bought closedcisc.com after I wrote that line today and had a chuckle | 19:40 |
| @juliusb | i was trying to think of some other name we could use, like risccores.org or something maybe | 19:40 |
| @juliusb | start another mailing list there | 19:40 |
| olofk | :) | 19:40 |
| olofk | Hang on. I'll set up a BBS instead | 19:41 |
| @juliusb | haha | 19:41 |
| @juliusb | but I was joking of course | 19:42 |
| @juliusb | (just in case anyone thought I was serious) | 19:42 |
| @juliusb | what about opencor.es | 19:43 |
| @juliusb | :) | 19:43 |
| @juliusb | .sc is seychelles | 19:44 |
| @juliusb | could get openri.sc | 19:44 |
| @juliusb | :) | 19:44 |
| @juliusb | argh, 35 pounds per year for a .sc | 19:45 |
| olofk | A colleague at work asked if we could use the simulator exit codes instead of printing exit(0) at the end of the tests. I think it should be technically possible. Are there any reasons not to do that? | 19:47 |
| @juliusb | huh? simulator exit codes? | 20:00 |
| @juliusb | like, the actual exit code the simulator passes? | 20:00 |
| @juliusb | I've been wanting to use that for a while | 20:00 |
| @juliusb | I put in a patch to make or1ksim do that | 20:00 |
| @juliusb | for verilog sim, I'm not sure if it's possible | 20:00 |
| @juliusb | so i just made a little script to check for the exit(0) string or something | 20:01 |
| @juliusb | verilator, that should certainly be possible | 20:01 |
| olofk | I just found the answer myself. There's no verilog standard for it, but icarus supports it | 20:01 |
| olofk | I guess a script like you describe is the best solution | 20:01 |
| @juliusb | yeah, if I recall corectly it varies between the sims | 20:02 |
| @juliusb | modelsim may not allow you do do like $finish(1) and have the process finish with return code 1 | 20:02 |
| olofk | Something like that would require full compatibility between the common RTL sims, so parsing is probably easiest | 20:04 |
| @juliusb | beware peter gavin's newlib now has a l.nop 0xc which is silent exit | 20:04 |
| olofk | Oh no! A ninja exit. | 20:05 |
| @juliusb | you know what i'm looking forward to? having a bit in the implementation-specific registers area (proposed with or1k-1.0) which says if we're sim or FPGA | 20:06 |
| olofk | What for, really? | 20:09 |
| olofk | I have half a patch for the new version registers, btw. Should finish that of some day | 20:12 |
| @juliusb | gtg, ttyl | 20:20 |
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