IRC logs for #openrisc Thursday, 2012-11-22

@juliusbmmm, just spotted an interesting bug in some code executing02:12
@juliusbthe flag status isn't maintained across an exception02:12
@juliusbthat's in the software in ORPSoCv2/mor1kx-dev-env02:14
@juliusbhmm, making making ESR the same across exceptions fixes things02:21
@juliusbthat's dodgy :-/ how come I've never seen that before! I'm not quire what happens, to be honest, the only thing we have is timer exceptions firing, there shouldn't be anything else changing the ESR during the handling of that02:23
@juliusb(by making ESR the same, I mean maintining it, ie putting it on te stack and restoring it before l.rfe'ing)02:25
@juliusbmaybe an mor1kx pronto bug02:38
-!- X-Scale is now known as Guest600006:06
-!- Guest6000 is now known as X-Scale06:09
@stekernjuliusb: without relly giving the thing alot of thought, but isn't the flag decoupled from spr_sr here?09:34
@stekernI had a similiar bug when I moved the branches into decode stage, now I changed that to use spr_sr as the "current flag"09:35
-!- jeremy_bennett is now known as jeremybennett10:18
@juliusbjonibo: I didn't like your email man, Ruben has legitimate arguments against OpenCores but to protest this by going against something the community has chosen to do (ie. cross-post until we have a single list) then it's just disruptive to anyone signed up to the OpenCore list only13:08
@juliusband we're going to ask him to stop it13:09
@juliusbI think that's reasonable13:09
@juliusbbut to say he's right in what he's doing isn't constructive13:09
@juliusbTBH i like the lists because they were there first and that's also the domain the OR1K Linux stuff is on13:11
@juliusbit's no problem, I think, to point to a list which is for the OpenRISC project, but also I don't care which way it goes if we finally end up with a single list13:12
_franck_olofk: I updated the patch here:
_franck_you can apply it15:08
@juliusbso, looks like old diez got a bit pissed off with us arguing over the mailing lists again15:40
@juliusboh well15:40
@juliusbbut if this is us about asking him to use both lists, then too bad I guess15:50
jeremybennettjuliusb: sometimes it has to be said. If only we could get the two lists merged, the problem would go away.16:12
jeremybennettThe trouble is both sides agree to a merger, so long as their list is the one that remains!16:12
_franck_let's create a third one :)16:13
@juliusbhaha, that may almost work :P16:22
@juliusbcheck that website sometime later ;)17:09
olofkAbout the mailing list discussions today, I just have to say, what a fucking drama queen!18:23's too much for me. I need to take a timeout from the project18:24
olofkhaha. I like :)18:26
olofkCan't find any whois info on it18:26 a wb master required to deassert stb the cycle after it sees ack from the slave, or can it wait a couple of cycles?19:07
@juliusbolofk: I agree, if he can't take us complaining about him as much as he complains about us, then so be it19:38
@juliusbi emailed him off list asking what he meant by "doing something I asked for"19:39
@juliusbolofk: I bought after I wrote that line today and had a chuckle19:40
@juliusbi was trying to think of some other name we could use, like or something maybe19:40
@juliusbstart another mailing list there19:40
olofkHang on. I'll set up a BBS instead19:41
@juliusbbut I was joking of course19:42
@juliusb(just in case anyone thought I was serious)19:42
@juliusbwhat about opencor.es19:43
@juliusb:)19:43 is seychelles19:44
@juliusbcould get openri.sc19:44
@juliusbargh, 35 pounds per year for a .sc19:45
olofkA colleague at work asked if we could use the simulator exit codes instead of printing exit(0) at the end of the tests. I think it should be technically possible. Are there any reasons not to do that?19:47
@juliusbhuh? simulator exit codes?20:00
@juliusblike, the actual exit code the simulator passes?20:00
@juliusbI've been wanting to use that for a while20:00
@juliusbI put in a patch to make or1ksim do that20:00
@juliusbfor verilog sim, I'm  not sure if it's possible20:00
@juliusbso i just made a little script to check for the exit(0) string or something20:01
@juliusbverilator, that should certainly be possible20:01
olofkI just found the answer myself. There's no verilog standard for it, but icarus supports it20:01
olofkI guess a script like you describe is the best solution20:01
@juliusbyeah, if I recall corectly it varies between the sims20:02
@juliusbmodelsim may not allow you do do like $finish(1) and have the process finish with return code 120:02
olofkSomething like that would require full compatibility between the common RTL sims, so parsing is probably easiest20:04
@juliusbbeware peter gavin's newlib now has a l.nop 0xc which is silent exit20:04
olofkOh no! A ninja exit.20:05
@juliusbyou know what i'm looking forward to? having a bit in the implementation-specific registers area (proposed with or1k-1.0) which says if we're sim or FPGA20:06
olofkWhat for, really?20:09
olofkI have half a patch for the new version registers, btw. Should finish that of some day20:12
@juliusbgtg, ttyl20:20

Generated by 2.15.2 by Marius Gedminas - find it at!