| stekern | hmm, wonder if it's possible to get the github pull requests directed to the mailing lists? | 08:04 |
|---|---|---|
| stekern | on a completely seperate matter, think I've got the muclibc/mglibc flag mess somehow sorted out at last | 08:08 |
| stekern | from what I've understood, the only thing the whole defining an own TARGET_HANDLE_OPTION was to emit a __UCLIBC__ define when uclibc was used | 08:10 |
| stekern | +did | 08:10 |
| stekern | and rejected mglibc, but since we should be able to support that long term, I don't see the point of doing that anymore | 08:14 |
| stekern | https://github.com/skristiansson/or1k-gcc/commit/8750ecc93fdf6563c4bf5d6280181e80ead39c2b | 08:15 |
| juliusb | opencores still down huh? | 13:10 |
| LoneTech | does look a bit unresponsive. I'll ask. | 13:13 |
| jeremybennett | good news on Adapteva. I see they closed on just under $900k. | 13:56 |
| jeremybennett | Look forward to getting that first Parallella board | 13:56 |
| jeremybennett | My reward also includes 8 care Epiphany chips, so I'm open to suggestions on how to use them. | 13:57 |
| jeremybennett | s/care/bare/ | 13:57 |
| LoneTech | hello jeremybennett :) | 14:02 |
| jeremybennett | hi LoneTech | 14:03 |
| LoneTech | I'm still a bit short on ideas for custom builds with the epiphany, but I'd love to see a camera with it | 14:12 |
| LoneTech | imagine a module like cmucam which is not restricted to blob detection | 14:13 |
| jeremybennett | LoneTech: Well if you come up with a good project, let me know. I don't have the facilities to deal with bare metal processors. | 15:35 |
| LoneTech | I'm not sure I can come up with anything beyond a stackable module for interconnecting them. the parallella makes a rather good prototype base on its own | 15:45 |
| juliusb | so the parallella board comes with a zync FPGA too, which is where teh dual-core ARM9s come in hey? | 15:49 |
| juliusb | that's a pretty sweet board then | 15:49 |
| juliusb | for $99 that's awesome, in fact | 15:50 |
| juliusb | hmm only 17k LUTs on it, 35K flip-flops, pretty big I guess | 15:52 |
| juliusb | 240KByte block ram, not too shabby | 15:52 |
| juliusb | considering all your processing needs are provided for (unless you want to run OpenRISC, of course) it's a cool platform at that point | 15:53 |
| juliusb | and then you have that adapteva chip too | 15:53 |
| LoneTech | those are 6luts; it is not farfetched to run an openrisc on it too | 15:56 |
| juliusb | no, certainly not, you could run a few - mor1kx variants use up to 5kLUTs I believe | 16:11 |
| gxti | is the zynq one really $99? it looked like they had a 'version 3' and a 'version 4' and maybe they were being a little unclear with which specs went with which price | 16:46 |
| jeremybennett | gxti: I think v3 and v4 refer to the 16-core and 64-core epiphany chips | 16:50 |
| LoneTech | gxti: the difference is in the epiphany chip only (64 cores vs 16 cores, smaller feature geometry), the zynq is the same | 17:08 |
| LoneTech | the Epiphany III is 16 core 65nm, while Epiphany IV is 64 core 28nm | 17:10 |
| LoneTech | same package, probably board compatible, though the IV has a lower top frequency according to the product page | 17:11 |
| olofk | Build support in orpsocv3 is coming along nicely. | 21:18 |
| juliusb | olofk: great! | 21:25 |
| juliusb | can anyone shed some light on why icarus verilog might just loop forever in a simulation? | 21:25 |
| juliusb | I can understand if I had put in a serious combinatorial loop and it just sat there forever evaluating it | 21:25 |
| juliusb | but, I've put an additional signal into the calculation of a synchronous signal and the sim freezes at a certain point :( | 21:26 |
| olofk | juliusb: I get that sometimes in VHDL when I have a process that isn't clocked and changes a signal that is in the sensitivity list of the process | 21:26 |
| juliusb | hmm i think it's not that | 21:28 |
| juliusb | it's verilog | 21:28 |
| olofk | Code, or GTFO | 21:28 |
| juliusb | :) | 21:29 |
| olofk | But you could get the same thing in verilog, like "always sig <= ~sig", when you meant always @(posedge clk) | 21:29 |
| juliusb | http://pastie.org/5133867 | 21:32 |
| olofk | Have you tried changing @* to @(next_insn_opcode or flag_i or flag_clear_i or flag_set_i) ? | 21:37 |
| juliusb | yep | 21:37 |
| juliusb | also tried changing that signal to a wire and doing it in an assign statement | 21:37 |
| juliusb | it can't be to do with that | 21:37 |
| olofk | Would be interesting to give it a run through modelsim. That could tell you if it's a icarus bug | 21:39 |
| juliusb | mmm i'm almost certain it'd work in modelsim | 21:39 |
| olofk | Is OR_ASYNC_RST set? | 21:39 |
| juliusb | nope | 21:40 |
| olofk | Can't find anything strange. | 21:43 |
| juliusb | ya trying it with modelsim now | 21:43 |
| olofk | Does it work? | 21:44 |
| juliusb | will let you know | 21:44 |
| olofk | Hmm.. has anyone else noticed that modelsim complains about or1200_genpc.v? | 22:00 |
| juliusb | ah same error, but this time it bails out | 22:00 |
| juliusb | # ** Error: (vsim-3601) Iteration limit reached at time 1910 ns. | 22:00 |
| olofk | Interesting. | 22:00 |
| olofk | Can you post the whole module? | 22:00 |
| juliusb | so.... I don't get it! | 22:00 |
| juliusb | sure | 22:00 |
| juliusb | http://pastie.org/5133992 | 22:01 |
| olofk | Was it line 311? | 22:03 |
| juliusb | didn't give a line number | 22:05 |
| juliusb | just listerally gave me that line and bailed out | 22:05 |
| juliusb | at least the errors are conssitent | 22:05 |
| juliusb | consistent | 22:05 |
| olofk | But you said that it appeared when you added a signal to a line. Which one was that? | 22:05 |
| juliusb | oh umm | 22:06 |
| juliusb | line 172 | 22:06 |
| juliusb | added the final "& !next_insn_will_branch" | 22:06 |
| olofk | got it | 22:06 |
| olofk | I have no idea | 22:16 |
| juliusb | :( me too | 22:18 |
| juliusb | it's so annoying that they give you no diagnostics basically | 22:18 |
| olofk | I would suggest a $display in every process just to see what goes on | 22:18 |
| olofk | But does it work for a while until it bails out? | 22:18 |
| olofk | You could set some breakpoints in modelsim and single-step too | 22:19 |
| juliusb | i did that too | 22:19 |
| juliusb | well, i put breakpoints on bits and pieces in that file | 22:20 |
| juliusb | somehow it's no thtat | 22:20 |
| olofk | What happens at 1910 ns? Reset release? | 22:22 |
| juliusb | nope | 22:38 |
| juliusb | dunno, to be honest | 22:38 |
| juliusb | some branch condition | 22:39 |
| juliusb | hmm i changed seemingly unrelated logic and it's unstuck | 22:47 |
| juliusb | :( | 22:47 |
| juliusb | to be fair the hacks I'd started on were at a fairly early stage of a rather large set of changes | 22:48 |
| juliusb | so, i figured I'd forge on and think through what I needed, and lo-and-behold it somehow got it out of the broken state | 22:48 |
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