IRC logs for #openrisc Monday, 2012-10-29

stekernhmm, wonder if it's possible to get the github pull requests directed to the mailing lists?08:04
stekernon a completely seperate matter, think I've got the muclibc/mglibc flag mess somehow sorted out at last08:08
stekernfrom what I've understood, the only thing the whole defining an own TARGET_HANDLE_OPTION was to emit a __UCLIBC__ define when uclibc was used08:10
stekernand rejected mglibc, but since we should be able to support that long term, I don't see the point of doing that anymore08:14
juliusbopencores still down huh?13:10
LoneTechdoes look a bit unresponsive. I'll ask.13:13
jeremybennettgood news on Adapteva. I see they closed on just under $900k.13:56
jeremybennettLook forward to getting that first Parallella board13:56
jeremybennettMy reward also includes 8 care Epiphany chips, so I'm open to suggestions on how to use them.13:57
LoneTechhello jeremybennett :)14:02
jeremybennetthi LoneTech14:03
LoneTechI'm still a bit short on ideas for custom builds with the epiphany, but I'd love to see a camera with it14:12
LoneTechimagine a module like cmucam which is not restricted to blob detection14:13
jeremybennettLoneTech: Well if you come up with a good project, let me know. I don't have the facilities to deal with bare metal processors.15:35
LoneTechI'm not sure I can come up with anything beyond a stackable module for interconnecting them. the parallella makes a rather good prototype base on its own15:45
juliusbso the parallella board comes with a zync FPGA too, which is where teh dual-core ARM9s come in hey?15:49
juliusbthat's a pretty sweet board then15:49
juliusbfor $99 that's awesome, in fact15:50
juliusbhmm only 17k LUTs on it, 35K flip-flops, pretty big I guess15:52
juliusb240KByte block ram, not too shabby15:52
juliusbconsidering all your processing needs are provided for (unless you want to run OpenRISC, of course) it's a cool platform at that point15:53
juliusband then you have that adapteva chip too15:53
LoneTechthose are 6luts; it is not farfetched to run an openrisc on it too15:56
juliusbno, certainly not, you could run a few - mor1kx variants use up to 5kLUTs I believe16:11
gxtiis the zynq one really $99? it looked like they had a 'version 3' and a 'version 4' and maybe they were being a little unclear with which specs went with which price16:46
jeremybennettgxti: I think v3 and v4 refer to the 16-core and 64-core epiphany chips16:50
LoneTechgxti: the difference is in the epiphany chip only (64 cores vs 16 cores, smaller feature geometry), the zynq is the same17:08
LoneTechthe Epiphany III is 16 core 65nm, while Epiphany IV is 64 core 28nm17:10
LoneTechsame package, probably board compatible, though the IV has a lower top frequency according to the product page17:11
olofkBuild support in orpsocv3 is coming along nicely.21:18
juliusbolofk: great!21:25
juliusbcan anyone shed some light on why icarus verilog might just loop forever in a simulation?21:25
juliusbI can understand if I had put in a serious combinatorial loop and it just sat there forever evaluating it21:25
juliusbbut, I've put an additional signal into the calculation of a synchronous signal and the sim freezes at a certain point :(21:26
olofkjuliusb: I get that sometimes in VHDL when I have a process that isn't clocked and changes a signal that is in the sensitivity list of the process21:26
juliusbhmm i think it's not that21:28
juliusbit's verilog21:28
olofkCode, or GTFO21:28
olofkBut you could get the same thing in verilog, like "always sig <= ~sig", when you meant always @(posedge clk)21:29
olofkHave you tried changing @* to @(next_insn_opcode or flag_i or flag_clear_i or flag_set_i) ?21:37
juliusbalso tried changing that signal to a wire and doing it in an assign statement21:37
juliusbit can't be to do with that21:37
olofkWould be interesting to give it a run through modelsim. That could tell you if it's a icarus bug21:39
juliusbmmm i'm almost certain it'd work in modelsim21:39
olofkIs OR_ASYNC_RST set?21:39
olofkCan't find anything strange.21:43
juliusbya trying it with modelsim now21:43
olofkDoes it work?21:44
juliusbwill let you know21:44
olofkHmm.. has anyone else noticed that modelsim complains about or1200_genpc.v?22:00
juliusbah same error, but this time it bails out22:00
juliusb# ** Error: (vsim-3601) Iteration limit reached at time 1910 ns.22:00
olofkCan you post the whole module?22:00
juliusbso.... I don't get it!22:00
olofkWas it line 311?22:03
juliusbdidn't give a line number22:05
juliusbjust listerally gave me that line and bailed out22:05
juliusbat least the errors are conssitent22:05
olofkBut you said that it appeared when you added a signal to a line. Which one was that?22:05
juliusboh umm22:06
juliusbline 17222:06
juliusbadded the final "& !next_insn_will_branch"22:06
olofkgot it22:06
olofkI have no idea22:16
juliusb:( me too22:18
juliusbit's so annoying that they give you no diagnostics basically22:18
olofkI would suggest a $display in every process just to see what goes on22:18
olofkBut does it work for a while until it bails out?22:18
olofkYou could set some breakpoints in modelsim and single-step too22:19
juliusbi did that too22:19
juliusbwell, i put breakpoints on bits and pieces in that file22:20
juliusbsomehow it's no thtat22:20
olofkWhat happens at 1910 ns? Reset release?22:22
juliusbdunno, to be honest22:38
juliusbsome branch condition22:39
juliusbhmm i changed seemingly unrelated logic and it's unstuck22:47
juliusbto be fair the hacks I'd started on were at a fairly early stage of a rather large set of changes22:48
juliusbso, i figured I'd forge on and think through what I needed, and lo-and-behold it somehow got it out of the broken state22:48

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