IRC logs for #openrisc Saturday, 2012-10-20

stekernhmm, seems like inetd takes ~100% cpu when or1k linux is running under qemu07:27
stekerncould it be the ethmac in qemu that is acting up?08:17
juliusbwhat happens if you disable that...?12:23
stekernkillhupping inetd seems to "solve" it12:28
juliusband was that responsible for slow execution of qemu?12:29
stekernfunctionally it looks pretty good at least, went through the gcc regression12:29
stekernyes, but I haven't really tested if it's much faster after the killhup12:30
stekernjuliusb: what was the critical path you saw on cappucino?12:59
stekernI'm seeing it in the pipeline forward logic13:02
stekernand iirc, that's where I saw it on milkymist too13:03
stekernor, I think it's the pipeline forward logic13:03
stekernit's from rf into rf13:03
juliusbthey're the 2 runs on virtex 5 I did, in the 2 configs13:04
juliusbone with multiply and one without13:04
juliusbone is from the RF, through the ALU, calculating an address for the LSU which then goes into the data cache13:04
juliusbfair enough13:04
juliusbthat'd be easy enough to register, imposing a cycle latency on the dcache lookups13:05
juliusbmmm, maybe I had caches turned off in the "smaller" implementation13:06
juliusblet me check13:06
juliusbyeah, cache disabled in teh first pastie\13:06
juliusbhence path is different13:06
juliusbthat's spartan6, with cache and multipliers13:07
juliusbdifferent path again13:07
stekern <- I don't quite get that14:26
stekernwhy is it going through lsu into the icache?14:26
juliusbumm lsu valid signal (which can stall the execute stage) going through teh control unit and controlling whether the fetch stage should advance14:51
stekernah, right15:01
stekernjuliusb: I just boldly deleted 32 lines of code, hope you will not miss'em too much ;)16:21
juliusbnps :) all cappuccino-specific stuff, so I guess if that still passes regression then all good16:35
stekernyeah, you could probably rip that out in espresso too, the signals are just dangling16:37
juliusbthere's a bit of that around the place17:10
juliusbwe also should factor out the tick timer and pic logic from the ctrl stages to neaten things up17:10
stekernmmm, and look into what more could be made generic17:38
stekern(I don't think there was a difference between the espresso rf and cappocino rf before I just ripped out those 32 lines)17:38
stekernit has to be done with consideration though, if you try to make it too much generic changes to one pipeline might break others otherwise17:39
stekernI take back what I said about rf, there are some other differences17:49
juliusbyeah im pretty sure there's differnces, otherwise I would have kept them separate to keep with the mission statement of module reuse within the processor18:27
juliusbok, now i have a hack to mor1kx-dev-env to allow you to point a variable to the GCC source directory and it will build and run all of the c torture tests19:03
juliusbwill rely the newlib startup code etc19:03
juliusbobviously it's not doing all of the testing of the gcc testsuite because there's a lot of stuff per test which will test different compiler optimisations19:04
juliusbbut i'm just interested in getting a bucketload of C code to run on the processor19:04
juliusbso something like: make vlt-tests GCC_TESTS=1 GCC_SRC=/localhome/jules/git/openrisc/or1k-gcc19:06
juliusbwill run the verilator model against each file19:06
juliusb1200-odd tests19:06
juliusbbetter than nothing :)19:06
stekernhow does that look?19:09
stekernI'm mostly wondering about the generate logic, functionality I have already tested19:10
juliusbyeah cool, adding a ffl1 registering stage, and thus valid signal? np19:10
juliusbcan you name the ffl1 wire ffl1_result?19:11
juliusbhmm or like19:11
stekernyeah, sure19:12
juliusbwas that a long path you were seeing?19:12
stekernon cyclone iv it's the most critical path19:13
juliusbfair enough19:13
juliusbwith cache enabled?19:13
juliusbi love looking at or1knd disassembly :)19:13
juliusbso much nicer than having all those delay slots19:13
stekernboth with and without19:14
juliusbah intersting19:18

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