IRC logs for #openrisc Sunday, 2012-03-04

unicosfor somebody new to OpenRISC, which is the best way to dive into getting a system running on hardware? orpsoc? minsoc? is one preferred?05:40
unicosI have had success with getting the uart.or32 example running through gdb remote on my terasic de0-nano containing minsoc, but haven't had any success loading u-boot05:42
stekernunicos: what's the problem with u-boot?07:06
unicosstekern: while loading u-boot over remote gdb, I get WB bus error during burst write and a CRC error- I'm confused because while this seems like a common problem on the FAQ, I can actually run the uart.or32 demo correctly09:08
unicosare there any known issues with programming and attaching the jtag bridge through a virtual machine? my development environment is a Fedora 16 VM...09:10
unicosI'll try to test from a real system later to help isolate my problem09:12
unicosI also tried booting the linux kernel with the same results- it transfers a little bit and the jtag bridge fails09:17
jonibo_juliusb: consider that your pending interrupt is for some realtime process... you shouldn't be delaying it even a single instruction... and it seems strange that a process should be making forward progress, one instruction at a time, during an interrupt storm... I agree with stekern that it's implied, but such is reading between the lines!09:38
jonibo_If I were to write software relying on such a feature (slow forward progress), then you're free to put me down quietly... :)09:39
stekernunicos: people seem to have all sorts of problems with adv_debug_sys on altera devices, so do I but you can try the orpsocv2 deà nano port at git:// and see if you have better luck with that10:09
derRichardhow do i compile openrisc 1200? (i know not much about verilog). is there a compiler which creates a binary blob? how can i program this blob into my fpga?13:58
stekernderRichard: you had that ordb2a board, right?14:00
stekernso that's an altera device, so you need alteras quartus tool to "compile" it into a bitstream14:01
stekernand then I believe urjtag is to be used to program that into the fpga14:02
derRichardokay. i fear the altera tool is not free, right?14:02
stekernit's free, but not open14:03
derRichardfree as free beer :(14:03
stekernfree of charge14:03
stekernyeah ;)14:03
derRichardokay. and what about ork1sim? let's say i change openrisc (like adding a new opcode...) how can i get this into ork1sim?14:04
stekernI can't say I'm all to familiar with the inner workings of or1ksim, so I guess my advice there is to dig around in the code, or ask Jeremy Bennett about it14:08
stekernbut for adding op-codes, there are a small set of "custom" instructions that are designed to used for that14:09
stekern*to be14:09
stekernl.cust1 - l.cust814:11
stekerniirc there is even an example l.custX implementation in or120014:15
derRichardthx a lot :)14:15
derRichardopenrisc is really cool stuff14:15
derRichardcontains r0 always zero?18:59
stekernit's implementation specific, but sw should never write anything else than 0 to it19:05
stekernso the short answer is: yes ;)19:05
derRichardi'm reading but it does not say anything about r019:12
stekerntake a look at the arch spec instead19:13
derRichardthe or1000 spec?19:15
stekernbut for or1200, it is a normal register just like any other19:17
derRichardbut it's also on or1200 always 0?19:20
stekernas long as you don't write anything else than zero to it, yes19:20
derRichardotherwise t  #define CLEAR_GPR(gpr) l.or    gpr,r0,r019:22
derRichardotherwise this would be wrong: #define CLEAR_GPR(gpr) l.or    gpr,r0,r019:22
derRichardi found this in the linux port and got confused19:22
stekernyeah, as a programmer, you can safely assume that r0 is always zero19:23
stekerni'm just pointing out that it's technically nothing special about r0 in or120019:24
stekernit's not hardwired to zero19:24
derRichardand where is it set to zero?19:32
juliusbthe arch spec says it shpuld always be read as zero and you should never wrote it19:38
derRichardif it's not wired to zero who takes care of it?19:39
juliusbbut on or1200 it should br written as 0 at the beginning19:40
derRichardat the beginning of what? does the assembler create such an instruction?19:43
jt_eatonwhat beginning? does the hardware clear it in reset or does the boot code have to write it? If I implement the registers as a bank or ram then it can be real hard to make sure r0 is never non zero19:43
stekernno, as the first instruction in reset vector19:44
juliusbhw doesnt clear ot, its isually in a register file whoch is a RAM which you cant reset19:45
juliusbso ypu must l.movhi r0, 0 as first insn19:45
jt_eatonno but I can force the ram address and data to zeros during reset with a active write so that r0 will be cleared by hardware coming out of reset. You still have the problem of someone writing a nonzero value with code19:47
juliusbyou could mask that easily enough bit i arfue its unecessary19:48
jt_eatonDo you want a robust design or a house of cards?  This is the type of thing that can easily create havoc in a large design team. All you have to do is forget to initialize r0 or overwrite it and you have a disaster.19:52
juliusbyeah well surely you understand the design ypure using19:54
jt_eatonI would argue that if the arch spec says always zero then it should be enforced by hardware. You dont want to have any more failure opportunities if you can prevent it19:55
juliusbi dont accept that you csnt introduce things like this to avoid hw complexity19:55
stekernthe arch spec doesn't say it is always zero19:56
jt_eatonwhat does it say?19:56
juliusbi cantget it right now (on phone)19:57
stekernR0 is used as a constant zero. Whether or not R0 is actually hardwired to zero is implementation dependent. R0 should never be used as a destination register.19:57
jt_eatonOK, Ill do some research19:58
juliusbbut iys basically some gates you can save by doing something simple in sw and wou;d be eyasy to denug19:58
stekern"R0 is used as a constant zero. Whether or not R0 is actually hardwired to zero is implementation dependent. R0 should never be used as a destination register."20:00
jt_eatonDont worry about saving gates, they are really cheap. Designer time is expensive.  It may only take 15 minutes to debug but that is how schedules slip20:00
stekernforgot the quotes around that, it's from the arch spec20:01
unicosstekern: thanks for the advice20:38
olofkWe talked about this before, and I really think we should update the implementation so that r0 is wired to zero. jeremybennett said that it could break legacy code, and that is true, but for me it seems like a bad thing from a security perspective to have it the way it is. What happens if some code reads from r0 and compares it to the current uid to check if root is logged in? Any process could just write something to r0 and we s20:50
olofkuddenly have a root escalation problem.20:50
olofkNot sure if that example would really work, but it still seems like a potential problem to me20:53
unicossuppose it helps if I'm in the right directory! I was trying to compile from orpsoc/boards/altera/de0_nano/syn/quartus/bin instead of .../run and getting all kinds of errors21:23
unicosstekern: using stefan's orpsoc for de0-nano, I can successfully program the device, but adv_jtag_bridge reports a lot of CRC errors and gdb fails to attach to the remote target with "Remote failure reply: E01"21:42
stekernpeople have succesfully commented out the CRC checking code in adv_jtag_bridge and got it working reliably21:43
stekernwhen I tested it I got the behaviour you are describing in about 33% of the cases21:45
unicosstekern: do you also use de0-nano?21:45
stekernyes I have a de0-nano21:47
stekern<- stefan21:47
unicosI've been using `./adv_jtag_bridge -b ./ ft245` with some success under minsoc, but the usbblaster cable option has never worked for me21:47
unicosah, hello!21:47
stekernyup, that's the same thing I have experienced21:48
stekernI think the ft245 option superseeds the usb-blaster one21:48
unicosgood to know- I have next to no experience with FPGAs and running things on them, so I've been assuming all problems are just my lack of understanding21:50
stekernI'd like to get those adv_debug_sys problems sorted out, I'm mostly using an external jtag-adapter whn connecting to the de0-nano (the "legacy" debug if), but using the builtin jtag-port really lowers the entry threshold for people 21:53
unicosI see21:59
unicosmaybe I should study verilog and the quartus toolchain in the mean time22:01
unicosI have no idea how to extend the project once I manage to get it running :)22:04
derRichardcan r0 be written in unprivileged mode? (i know changing r0 is bad)23:40

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