IRC logs for #openrisc Monday, 2012-02-27

-!- Flea86 is now known as flea86|away03:02
-!- flea86|away is now known as flea86|soldering03:35
-!- flea86|soldering is now known as flea86|away04:00
flea86Just curious, but is there a *complete* list of all the asic chips available that contain an openrisc core?09:29
Lampus|2Hm.. I'm interesting in such list too09:30
flea86Don't know if the other folks here are aware of this, but there's an appotech SOC that contains an openrisc core! XD09:31
flea86100MIPS of open-source asic goodness :P09:32
Lampus|2What tech process has been used by appotech?09:37
Flea86_got disconnected :S09:37
Lampus|2Flea86_:  What tech process has been used by appotech?09:38
Flea86_Lampus: Good question! I've never asked them tbh09:39
-!- Flea86_ is now known as Flea8609:39
Lampus|2Flea86: do you talk about this chip: ?09:40
Flea86Lampus|2: No, but I suspect that it too is openrisc :309:41
Lampus|2According to line "Input Voltage: 1.6-2.0" I can suggest that they used 0.18um tech process09:41
Flea86funny, that used to say *openrisc*09:43
Lampus|2I have a new problem. I have replaced onchip_ram to wishbone SDRAM controller.12:16
Lampus|2adv_jtag_bridge Self-test PASSED successfully12:17
Flea86I wish I could help you there Lampus|2, but I don't do any fpga stuff at this time.. :(12:18
Lampus|2But when I trying to start 'hello world ' program, CPU is freezing12:19
stekernLampus|2: how are you loading the program?12:22
Flea86Lampus|2: What is your sdram frequency? have you tried just reading/writing data to/from the sdram?12:22
Lampus|2stekern: using gdb with 'load' command12:22
Lampus|2Flea86: I tried several frequencies. For now it's 50 MHz for wb_clk and sdram_clk12:23
Lampus|2*have tried12:24
stekernyou had it working with the onchip ram?12:25
Lampus|2$ adv_jtag_bridge -a 1 -l 0:10 -l 1:4 -t usbblaster12:25
Lampus|2Found Altera USB-Blaster12:25
Lampus|2Found Altera USB-Blaster12:25
Lampus|2firmware version = 0x0004 (4)12:25
Lampus|2Enumerating JTAG chain...12:25
Flea86stekern: He did12:26
Lampus|2Hm. I was dropped from IRC. Seems this IRC server don't like very long messages =)12:27
stekernpastebin loves long messages ;)12:27
Lampus|2stekern: yeah, I know. One second, please12:28
Lampus|2With onchip_ram all worked fine12:31
stekernwhat sdram controller are you using?=12:33
Lampus|2After interrupting 'continue' command I have 'Remote failure reply: E01' error message12:33
Lampus|2And in adv_jtag_bridge output: ""Error while reading all registers: 'CRC mismatch'12:34
Lampus|2CRC ERROR! Computed 0xb792881a, read CRC 0x1846ef3312:34
Lampus|2Retry count exceeded!  Abort!12:34
Lampus|2 12:34
Lampus|2Error while reading all registers: 'CRC mismatch'12:34
Lampus|2Any ideas?12:38
Flea86buy an openrisc asic? :P12:41
* Flea86 runs12:42
Lampus|2It's not very good idea12:42
Lampus|2I need my own ASIC =)12:43
Lampus|2based on OpenRISC, of course =)12:44
stekernwhat sdram controller are you using?12:46
Lampus|2stekern: as I have already said before,sdr_ctrl12:47
stekernah, sorry I missed that line :)12:49
Flea86stekern: I always thought that any module that was truly 'wishbone compliant' just worked and that's it, right?12:51
Lampus|2I have terasic DE0 board with Zentel SDR SDRAM 64Mbit with data width 16 bit, 12 bit row addr, 8 bit column addr, 4 banks12:52
Flea86physical hardware considerations aside, ofc :312:52
stekernFlea86: yes, it should just work12:53
stekernof course, it could lack support of some features such as bursting etc12:53
Flea86Lampus|2: I have similar (tmtech/etron) sdram chips on my flea86 hardware.. :)12:54
Lampus|2But as I can see writing/reading of memory just works, and self-test passsed, but I can't run any program on it12:54
Flea86Lampus|2: does the sdram controller also support burst modes as well?12:55
stekernLampus|2: have you double checked your ibus connections?12:55
Lampus|2Flea86: how I can test it?12:56
Flea86openrisc also has a cache buffer, no?12:56
Lampus|2Flea86: do you mean data/instruction cache?12:57
Flea86Lampus|2: How, by running it in the expected (multiple?) sdram burst modes12:57
Flea86Lampus|2: Yes12:57
Flea86and performing 'block moves' of the sdram data, perhaps the Zentel parts require a specific setup? (never used them myself, but suspect they should just work)12:58
Lampus|2`define OR1200_DC_1W_8KB12:59
Lampus|2It's for ASIC12:59
Flea86Lampus|2: huh?12:59
Lampus|2`define OR1200_NO_DC12:59
Lampus|2So I don't have data/instruction caches13:00
Flea86stekern: Ah! try that now!!13:01
* abogani waves all13:01
Flea86one less variable in the equation :)13:01
aboganiCould anyone suggest me a cheap FPGA board which is capable of running Linux (on OpenRISC obviously)?13:01
aboganiThanks in advance!13:01
Flea86Hey abogani o/13:04
Flea86Wish I could help, but fpga's aren't exactly my strongpoint personally..13:05
stekernLampus|2: you shouldn't need to enable caches to get things rolling13:05
Flea86stekern: did you mean disable there?13:06
Lampus|2But caches are already disabled13:06
stekernFlea86: the wb-bursting should not be connected to the bursting of the sdram-controller, and it should work even if the sdram-controller didn't support wb-burst modes13:06
stekernno, I meant enable, it should work with a no-dc setup too13:07
aboganiFlea86: Thanks anyway :-)13:09
Lampus|2My SDRAM controller connection:
Lampus|2Any comments?13:10
stekernLampus|2: not much to comment when not knowing what those are connected to13:18
Lampus|2stekern: wb_ss_* - wires that were used before for onchip_ram. It's just default minsoc configuration in other parts13:20
stekernaha, ok, not that familiar with minsoc13:25
Lampus|2stekern: Flea86: WB SDRAM controller  that I'm using have wb_cti_i input (cycle type identifier), and I haven't connected it to something. Could it be source of problem?15:00
Lampus|2What about compability between different revisions of wishbone?15:01
Flea86Lampus|2: If that's an input to the sdram controller (wb_cti_i) then yes it could :)15:02
Flea86just like in real hardware, you need to define *all* input states (though in this case the compiler might be already doing it for you, but don't count on it)15:05
stekernLampus|2: have you looked at the sdram controllers code if it's used?15:06
stekern(afaict it's not)15:06
Lampus|2stekern: strange, but seems that wb_cti_i in sdram controller not used anywhere15:09
Lampus|2It's just declred as input in wb2sdrc module, but not used.15:11
juliusbthat appotech SoC looks very interesting18:27
juliusbthat may well be OpenRISC - I'd believe it18:27
juliusball the specs look right for the processor18:27
juliusbalthough, there's programmable priority18:28
juliusbnot sure OR1K has that18:28
juliusbgoogle cache hey?18:32
juliusbis loading slowly for me18:32
stekernwhy can't you easily get the direct link to the pdf easily from google?18:32
stekernanyways, that pdf says openrisc, it's ax300518:33
juliusboh yes indeed18:34
juliusbtick timer register is the same It hink18:35
stekernwould be fun to play with one of those18:36
juliusbit would indeeed18:36
juliusbit's from a couple of years ago18:37
juliusbso if it's 100 MIPS probably running at 100MHz then18:38
juliusbassuming roughly 1-clock per instructino for most instructions18:39
juliusbor maybe a little more, say 120 MHz18:39
juliusbthe PLL runs from 48-150MHz18:40
juliusbso maybe you can get it to 150MHz18:40
juliusbso if they've stuck with same RISC processor, they have a few other chips with it in, too18:42
stekernyeah, I'd guess the one flea86 posted probably has it too18:43
juliusbI contacted them asking for where we might buy them in europe or if they can mention any products containing them hehe18:49
juliusbwe'll see what response I get18:49
stekernheh, cool. they are fairly recent at least18:56
juliusbI think this is talking about a dev board which has the AX2008 on it:
stekernmin order 250019:01
juliusbhaha: "The company doing the chip, but very clever to avoid the patent. Now basically use the open source IP, such as IEEE802.3, USB 2.0, open RISC." from here:
juliusbsurely we could ask for some engineering samples19:02
juliusbno mention of MMU or using Linux on it19:02
juliusbNot sure google translate is correctly following the nuances of the language: "Taiwan's IC. Forget the development of electronic cockroach life all day is play of magical rotten tricks"19:06
stekernreminds of that old jeremy clarkson show where he goes to some tuning shop in japan19:09
juliusbthey could very well have bought this from beyond semiconductor, too19:09
stekernthey had just put all kinds of flashy english words on the rims19:10
juliusbhaha, "All over the physical ironic power"19:13
--- Log closed Mon Feb 27 22:16:09 2012
--- Log opened Mon Feb 27 23:24:39 2012
-!- Irssi: #openrisc: Total of 15 nicks [0 ops, 0 halfops, 0 voices, 15 normal]23:24
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