IRC logs for #openrisc Saturday, 2018-07-07

--- Log opened Sat Jul 07 00:00:46 2018
-!- [X-Scale] is now known as X-Scale11:27
shivm28[m]shorne: Hi, I have written a blog summarizing the details of the work accomplished during the second phase of the project.12:47
dunnousernamefnHey, so I was wondering how I can make multiple cores with the mor1kx core. It has a multi-core option, but I don't understand how I link cores together given the verilog files19:56
dunnousernamefnSpecifically, what busses/interfaces must be linked for the cores to be able to communicate between each other20:48
dunnousernamefnSo, from what I understand, OpenRISC processor cores all start at addr 0x100, and the only communication between them is in the memory interface; furthermore, special registers allow to determine the core number (almost like how the return value in fork() works). Is this correct?22:00
shorneshivm28[m]: thanks22:52
shornelet me have a look22:52
--- Log closed Sun Jul 08 00:00:47 2018

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