| --- Log opened Sat May 26 00:00:44 2018 | ||
| qogreycat | THIS IS AN EMERGENCY NOTICE THIS IS NOT SPAM: THIS NOTICE IS CURRENTLY GOING OUT TO ALL CHANNELS THROUGH THE FREENODE EMERGENCY NOTIFICATION SYSTEM: GRUMBLE HAS INADVERTENTLY NOT RESET THE FREENODE SECURITY PASSWORD CAUSING A BREAK IN FREENODE SECURITY WHERE ALL PASSWORDS HAVE BEEN RELEASED. PLEASE SEE GRUMLE IN #FREENODE FOR INFORMATION ON HOW TO SECURE YOUR ACCOUNT!! | 05:01 |
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| qogreycat | trem rohitksingh rah smaeul M6HZ X-Scale ZipCPU arnd _franck_ Marex cornu[m] stekern O01eg shorne mithro _florent_ marex-cloud Ishan_Bansal shivm28[m] Ekho mripard jfng kuhn mafm[m] clopez blueCmd LoneTech oleg-nenashev Guest96645 mwfc zama promach simoncook wbx nurelin awygle Finde juliusb heroux hansihe | 05:01 |
| FL4SHK | anyone here know if there's an IRC channel for Icarus Verilog? | 15:40 |
| FL4SHK | I need to use a particular esoteric feature of it | 15:40 |
| FL4SHK | but it's not working for some reason | 15:41 |
| FL4SHK | I know I can restructure my code for it, but I'm having to do trial and error to figure out what exactly the issue is | 15:41 |
| FL4SHK | it thinks I've used a "disable" statement somewhere when in my code there is no such thing | 15:41 |
| FL4SHK | (I'm trying to use the feature to convert the Icarus Verilog version of SystemVerilog to VHDL, trying to avoid having to rewrite my code in Verilog since the CAD tool I want to target supports mixed Verilog and VHDL, but not SystemVerilog at all) | 15:42 |
| FL4SHK | (and yes, like I said, this is esoteric as hecccc) | 15:43 |
| FL4SHK | finally got it working | 16:20 |
| FL4SHK | only really required one change | 16:20 |
| FL4SHK | ...okay it was actually more than that | 16:20 |
| FL4SHK | sorry about the wall of text | 17:50 |
| FL4SHK | I may ask some CPU development questions in the future :P | 17:51 |
| --- Log closed Sun May 27 00:00:45 2018 | ||
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