| --- Log opened Thu Oct 05 00:00:15 2017 | ||
| juliusb | regarding the best way to build a system, I like the idea of Python being used to describe the structural stuff, use its cleverness to autogenerate some portions of the design, but in reality not everyone is going to use components compatible with say Migen or <your system builder here>, that's why standards like IP-XACT (as clunky as it is) are key to aiding reuse, and I like the idea of top-levels and connectivity being stitched together according to IP-XACT. Instead of writing out verilog top-levels maybe Migen should write out IP-XACT descriptions, leaving another tool to do the toplevel generation and stitching which would then allow other off-the-shelf Verilog components to be used with greater ease. Register generation should almost certainly be done using that standard. Maybe I'm wrong, but I just so many tools trying to recreate piecemeal what IP-XACT already supports, and as much as XML sucks to edit remember you can easily generate it from other inputs, and we should maybe be focusing on IP-XACT tools | 00:17 |
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| mithro | juliusb: Did your message get cut off? | 01:33 |
| mithro | juliusb: Yes, I agree that not everyone is going to be using one technology so we do want to figure out how to share across language domains | 01:37 |
| mithro | juliusb: You should join #timvideos | 02:10 |
| mithro | shorne_ / juliusb: https://docs.google.com/spreadsheets/d/1pNunBJX46jp6ClPFZA29GhlXJmb9lnG9_BEVej7XxL4/edit#gid=1872227914 | 02:10 |
| mithro | Okay, this doesn't seem to make any sense -- how would disabling all the mor1k features mean it uses *more* resources? | 04:48 |
| stekern | mithro: define "disable all features" | 06:00 |
| mithro | stekern: I must have just being doing something wrong, I played with it and it started working | 06:01 |
| mithro | stekern: But if you are interested -> https://gist.github.com/mithro/c48be01ef38b49a1b12fa6ca8464bfb8#file-attempt3-disable-everything-patch | 06:01 |
| mithro | juliusb / shorne_: Running the mor1kx at 50MHz rather than 83.333MHz seems to affect the resource usage quite a bit. | 06:22 |
| juliusb | mithro: sure, that's reasonable | 08:48 |
| juliusb | mithro: my long opinion piece about python and flows wasn't cut off. I maintain that probably IP-XACT covers a lot of what we want to do in the way of IP assembly and auto-generated stuff, that we should probably stop inventing new ways of describing the stuff we want to build and generate and hack on tools which are compliant with the existing standards | 08:51 |
| juliusb | but in my experience *every* single company or project does it their own way which is a shame | 08:51 |
| mithro | what does "and I like the idea of top-levels and connectivity being stitched together according to IP-" mean? | 08:53 |
| juliusb | well, I think it's entirely reasonably flows and IP descriptions can be done in their own way (although I'm hoping something like FuseSoC could become a de-facto flow, but everyone needs to customize it a lot so it'd be hard to hvae a tool which supported every quirky setup under the sun) but for the basic stuff we all know we need, why keep reinventing the wheel is all I'm asking. | 08:53 |
| juliusb | So IP-XACT, among other things, can be used to define port lists and connectivity, and so why isn't it used more to describe how all of your cores are hooked up when you've got just a structural module? | 08:55 |
| juliusb | ie. a module which is just hooking up stuff to its ports, and the ports of the stuff it's instantiating | 08:55 |
| juliusb | at present a lot of it is done by hand or by some other bespoke tool. | 08:56 |
| juliusb | Kaktus can do this sort of stuff, if I am not mistaken | 08:56 |
| juliusb | It's interesting how migen takes this to the next level and wants to support logical expressions as well and auto-generate that, which is pretty cool. Actually, how do you write a state machine in migen? I'd be interested to see how that is done and the generated Verilog. | 09:01 |
| mithro | juliusb: You mean FSMs? https://github.com/enjoy-digital/litescope/blob/master/litescope/core.py#L131-L161 | 09:02 |
| mithro | Well, it's bed time for me, happy to give you my thoughts on the above another time | 09:08 |
| FL4SHK | mithro: Icarus Verilog has some support | 09:09 |
| FL4SHK | some support for SystemVerilog that is | 09:09 |
| FL4SHK | not nearly complete though | 09:10 |
| FL4SHK | I'd be really happy with the synthesizable subset alone | 09:10 |
| FL4SHK | It has some of that though | 09:11 |
| shorne_ | yay, done sending gdb patches again | 10:24 |
| shorne_ | now back to linux smp | 10:24 |
| mithro | If anyone in here is interested, we are running a TimVideos hackfest before LCA2018 here in Sydney, Australia -- We will no doubt be hacking on HDMI2USB, Migen/MiSoC, LiteX, mor1kx and similar things -- LCA2018 will also be having a day long "Build your own SoC to run linux (using LiteX + mor1kx)" tutorial event.... -- If you think you might possible want to come can you fill out this form so we can understand how | 16:07 |
| mithro | much funding / sponsorship we need to source for flights / accommodation / etc -> https://goo.gl/forms/1FI041Iat7LgQA9N2 | 16:07 |
| mithro | stekern: Don't know where in the world you are but apparently I should encourage you to come to the above! -^ | 16:08 |
| --- Log closed Fri Oct 06 00:00:17 2017 | ||
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