| --- Log opened Sun Sep 24 00:00:59 2017 | ||
| mtn2 | shorne: I am more worried about connecting to debug unit. I see they are specific to target FPGA for the de0Nano version of the core. (Sorry for the delayed reply- it was long weekend here) | 02:30 |
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| mtn2 | DDR controller is not a problem. I do have old version of Bexys4 which is without DDR | 02:32 |
| -!- [X-Scale] is now known as X-Scale | 04:01 | |
| mtn2 | Wondering what is the max clock speed attained (expected) for mor1kx for ASIC (please mention which technology) implementation ? | 04:30 |
| shorne | mtn2: I wrote this tutorial about connecting to the debug unit with openocd, https://github.com/openrisc/tutorials/blob/master/docs/Debugging.md | 08:50 |
| shorne | it might not be the best since I just did it to note things I need to remember, but does that help? | 08:51 |
| shorne | I have always run mor1kx at 50mhz, its "good enough" for me, booting linux in about 3 second (after image load) | 08:51 |
| mtn2 | shrone: Thanks a lot. Let me go through your debug tutorial. | 09:28 |
| mtn2 | 50 Mhz in which fpga?. For ASIC I see 250 Mhz for 180nm 6 metal layer process. https://en.wikipedia.org/wiki/OpenRISC_1200#Performance . We have a 65nm library - if 250 Mhz is true for 180nm, then at 65nm should able to hit close to 1Ghz | 09:31 |
| --- Log closed Mon Sep 25 00:00:00 2017 | ||
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