IRC logs for #openrisc Sunday, 2017-09-03

--- Log opened Sun Sep 03 00:00:28 2017
shorne_stekern_: Hello, did you happen to see some of the comments on the ompic driver?04:52
shorne_The vendor question came up, maybe I will use 'openrisc,'04:53
shorne_But also, there was a question on memory barriers, i.e.04:54
shorne_   set_bit(irq, &ipi_data[dst_cpu].ops);04:55
shorne_   ompic_writereg(ompic_base, OMPIC_IPI_CTRL(src_cpu), data);04:55
shorne_Do we really need an l.msync in order for the memory write to be seen in all cores before the writereg gets seen by the IPI controller?04:57
shorne_ stekern_: as far as I can tell the l.swa/l.lwa imply a l.msync08:20
shorne_so I am thinking its not needed as long as I am using atomic stores08:20
stekern_shorne_: I think so too09:02
stekern_as for the vendor, openrisc sounds fine for me at least09:03
stekern_(although, it's not strictly tied to openrisc, you could hypothetically use it for any cpu core)09:04
stekern_but "openrisc" as in "it came out of the openrisc community"09:05
shorne_stekern: thanks, I will reply17:39
--- Log closed Mon Sep 04 00:00:30 2017

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