IRC logs for #openrisc Monday, 2017-07-10

--- Log opened Mon Jul 10 00:00:07 2017
promachstekern: why do you requires such large width as in ?00:03
stekernpromach: what do you mean? they're rams with 1024 entries06:32
promachstekern: I am referring to line 149, not line 15006:33
stekernso am I06:33
promachwhat is the purpose of trig_mem ?06:34
stekernto store the trigger data06:36
stekernit could have been included into the data_mem as well, but I choose to keep it separate06:37
promachwhat do you exactly mean by 'trigger data' ?06:42
promachstekern: I thought 'trigger' is a 'one-bit' signal06:46
stekernno, trigger can be up to 32-bit06:47
promachwhy do you need 32-bit for trigger signal ?06:48
stekernto be able to trigger on up to 32-bit data...06:50
promachhuh ? why would 'one-bit' trigger signal not be able to trigger on 32-bit data ?06:51
stekernyou feed the input with a 32-bit signal, then you compare that with what you want to trigger on06:51
stekerne.g. an address06:52
stekernso if you want to trigger on different addresses, 1-bit is not enough06:52
promachyour 32-bit trigger is actually based on address ?06:52
stekernno, it doesn't have to be an address, it was just an example06:53
stekernif you only need a 1-bit trigger, you can connect only one bit to trig_i06:54
promachstekern: my understanding of trigger is based on figure 5 of
promachseems like we have different ways to define trigger, just like we have different ways to trigger on analog waveforms in oscilloscope06:57
promachstekern: your definition is more on like triggering on i2c or spi address06:57
promachthat blog link is more like edge triggering at different point in time of the analog waveform06:58
stekernyeah, but it's the same thing... just that my ILA does an equality check on two values (an input and a choosen value) to generate the trigger event07:00
stekernrather than just taking a 1 bit input signal07:01
stekernthe former is a lot more practical, since you can then change the trigger condition without having to resynthesize the logic07:03
stekernyou could make it even more flexible by introducing another signal that would mask the bits you are interested in07:05
promachstekern: introducing another signal that would mask the bits you are interested in ??? could you elaborate more ?07:25
ZipCPUif (A==B) vice if ((A&MSK)==B)07:26
promachZipCPU: what MSK ?  what 'vice if' ?07:30
ZipCPUMSK and B in my example would be set by the user post-synthesis time.07:30
ZipCPUThe "vice" is an English term (not a Verilog term) to separate the two possibilities and show you the difference.07:30
promachhow is  " if (A==B) vice if ((A&MSK)==B) " being more 'flexible' ?07:32
ZipCPU"if ((A&MSK)==B)" is more flexible than "if (A==B)"07:33
promachflexible in what way ?07:33
promachZipCPU: I thought can  change the trigger condition without having to resynthesize the logic ?07:34
ZipCPURead the code.  MSK and B can be set via writing to a register.  Set MSK to -1, and you get "if (A==B)".  Set MSK to anything else, and you can do a bit-select on the input.07:34
ZipCPUNot as written.  wbscope requires an external trigger.  If you wish to change that external trigger, you'll either have to resynthesize or build a piece of logic allowing you to select from among whatever external triggers you would like to select from.07:35
stekern(just to note, my code does not do the mask thing, it was just a sidenote)07:35
stekernbut the condition can be changed at runtime07:35
promachstekern: ok      ZipCPU: external trigger ? so, why need to resynthesize ?07:36
promachthis is my initial top-level
ZipCPUIt's a start.07:39
promachZipCPU: could also change user trigger and user holdoff values at run-time, right ?07:40
ZipCPUCheck the spec.  What does the spec say about that?07:40
promachYou can even change the holdoff while the scope is running by writing a new holdoff value together with setting07:51
promachthe RESET n bit of the control register.07:51
promachand i_trigger is an input07:51
stekern...but you can't change the trigger condition at runtime...08:06
promachstekern: wait, are you referring to ZipCPU source code ?08:10
ZipCPUpromach: stekern's right.08:10
promachZipCPU: why cannot change the trigger condition at runtime ?08:10
ZipCPUAs built, you can't change the trigger condition at runtime.08:10
ZipCPUI haven't had a need to add that capability in.08:11
ZipCPUNeither can you change the data you are sampling at run time.08:11
ZipCPUIt's fixed with the build.08:11
ZipCPUWell, yes, you can "manually" trigger the scope.08:13
ZipCPUThat takes a bus interaction to do, but it is doable.08:13
promachSo, why cannot change the trigger condition at runtime ?08:13
promachI am just curious08:14
stekernpromach: because there's only a 1-bit trigger input08:14
stekernand that input needs to be 1 for the trigger event to happen08:14
stekernit's fixed to 1-bit and you can't change the polarity08:14
stekern...and that's been enough for ZipCPU08:15
promachi_trigger is either zero or one08:15
ZipCPUstekern: Well said, thank you.08:15
promachand it is an input to wbscope softcore08:15
stekernI needed to change the trigger condition at runtime, so I made it a 32-bit signal08:15
promach1-bit trigger  --> cannot change the trigger condition at runtime ??08:16
promach32-bit trigger  --> can change the trigger condition at runtime ??08:16
stekern.. and compare that to a runtime configurable value08:16
promachwhat about changing value of 1-bit i_trigger at run-time08:17
stekernif you have tree signals, a, b and c. How would you trigger on a=1, b=1 and c=1 with ZipCPU's scope?08:18
stekernhow would you configure it at runtime to trigger at a=1, b=1 and c=0?08:18
ZipCPUYou'd need an external LUT: scope_trigger <= (a)&&(b)&&(c);08:18
ZipCPUalways @(posedge i_clk) scope_trigger <= (a)&&(b)&&(!c);08:18
ZipCPUBut ... I think I'm proving stekern's point.08:19
promachI thought this is an external logic08:19
promachinstead to be done inside wbscope08:19
stekernwell... exactly, in wbscope you have to add external logic for it, in diila it is built in...08:20
promachI was thinking if the user could feed i_trigger <= (a)&&(b)&&(c); into wbscope08:21
promachwithout modifying wbscope08:21
ZipCPUOf course the user can ... but it would require you to re-synthesize your design.08:21
promachi_trigger is an input to wbscope08:22
ZipCPULikewise, you can change c to !c, but you'd still need to resynthesize the design--just like stekern is saying.08:22
promachright ?08:22
ZipCPUYes, i_trigger is an input to wbscope.08:22
promachresynthesise the design ? which design ?08:24
promachwbscope itself ?08:24
promachor blocks other than wbscope ?08:24
ZipCPUI am not aware of any synthesis tool that allows you to synthesize portions of your design without also resynthesizing the whole design.08:25
promachpartial reconfiguration08:25
ZipCPUI've been told they exist, but ... I am not aware of any.08:25
promachI mean I am just asking which blocks require a change08:25
stekernregardless, you have to resynthisize something08:26
ZipCPUThe only logic change is the line defining the scope's trigger.  Everything else can stay the same if you would like.08:26
stekern!= runtime08:26
promachstekern: ok, how would 32-bit helps to change in run-time ?08:28
stekernbecause then you can compare it against an at runtime user configurable value08:32
stekern...which is written to the module via the wishbone bus08:33
ZipCPUstekern: Out of curiosity, what use case has made your 32-bit trigger selector the most useful to you?08:38
stekernbecause that's the size of the data on the wb-bus08:38
stekern...i.e. 32-bit just matches the user configurable value08:39
ZipCPUSo ... do you trigger off of such things as when the bus has a write to (or read from) a particular address?  Is that how you would use it?08:40
stekernI quite often used it to match addresses, yes08:40
stekernso, I'd take the address and some control signals in the lsb, and trigger on that08:41
ZipCPUThat's a slick solution.  I like it, and I can see the application for it.08:42
promachZipCPU: I think for now, edge triggering is enough for me. I will go for stekern address triggering mode after this for i2c and SPI controller10:53
promachstekern: would your ILA be able to do something like Figure 1 of ?11:53
shornestekern: sorry, it looks like the discussion went in a different direction yesterday16:56
shorneI was looking a bit more into cache coherency issue16:56
shorneI noticed a few things, in PTE there is a bit for CC, it seems its always set (because it used to be used as PRESENT bit)16:57
shornehowever I am not so sure how its used in the RTL16:58
shorneThere seems to be a feature sdram address snooping.  used for both16:58
shorne  - Snooping dram access to ensure lwa/swa atomic operations are not invalidated by a secondary processor16:59
shorne  - Snooping dram access to clear lines written to by secondary processor16:59
shorne(but the later does not seen enabled by default)17:00
shorneany reason for that?17:00
shorneIn terms of the PTE/DTLBWyTRn [CC] bit I dont see it used for cache coherency17:12
shornein rtl/verilog/mor1kx_dmmu.v17:12
shorneMaybe you know better?17:12
--- Log closed Tue Jul 11 00:00:09 2017

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