IRC logs for #openrisc Friday, 2017-03-31

--- Log opened Fri Mar 31 00:00:08 2017
mithroIs the mor1k and or1200 instruction set the same?04:34
mithroAnyone here understand the mmu emulation stuff in qemu?05:36
bandvigmithro: (1) mor1kx and or1200 are just different implementation of the same architecture, so, ISA is also same for them. (2) Could not say nanything related MMU in QEMU.06:38
mithrobandvig: thanks, that is what I thought but wanted to check..07:01
shorne_mithro: I know a bit about mmu qemu, I have some patches waiting for next qemu merge cycle07:47
shorne_but really I just know the openrisc implementation, not general qemu much07:47
-!- shorne_ is now known as shorne07:48
mithroshorne: On the lm32 we have the ability for the processor to ignore the MSB, with reads that go to the upper half bypassing the cache07:49
mithroshorne: I'm trying to understand how I can add that to the openrisc emulation07:50
shornelet me have a look at lm32...07:52
shornecpu_lm32_set_phys_msb_ignore(env, 1);?07:53
shorneit seems that all lm32 does differnt when that is set is mask the hwaddress sent to tlb_set_page()08:00
shornetlb_set_page(cs, address, address & 0x7fffffff, prot, mmu_idx, ...08:00
mithroshorne: I don't necessarily understand everything yet :-P08:03
mithroshorne: As far as I understand though, if you access the values from one region you end up reading through the CPU's cache, if you access it from another you read it directly -- maybe in QEmu there is no emulation of the caching behaviour?08:04
mithroThe README in the target-lm32 says08:06
mithroSome SoC ignores the MSB on the address bus. Thus creating a shadow memory area. As a general rule, 0x00000000-0x7fffffff is cached, whereas 0x80000000-0xffffffff is not cached and used to access IO devices.08:06
mithroshorne: Doesn't look like the lm32 CPU has any icache/dcache emulation that I can see?08:11
shorneright, I dont know too much about it allso,  but what I see is this method is part of qemu core08:12
shorneits for setting the qemu internal TLB (maybe thats what you mean by cache)08:12
shornefor lm32 it doesnt look like there is really man mmu08:12
shorneso the address requested, is simply added to the tlb08:13
shorne  tlb_set_page ((virtual)addr, (physical)addr)08:13
shorneor if the msb ignore thing is set it does08:13
shorne  tlb_set_page ((virtual) addr, (physical)addr &07ffffffff)08:14
shorneIt dont see how that means its "ignored" really08:14
shornebut for openrisc with a mmu it doesn08:14
shorne cpu_openrisc_get_phys_addr((virtual)addr, &physical)08:15
shorne if (that worked)08:15
shorne  tlb_set_page ((virtual)addr, physical & PAGE_MASK)08:16
mithro -- Looks like we get the shadowing via setting the OPTION_DCACHE_LIMIT_WIDTH to 31 bits in the FPGA08:16
shorneright, so I think all you would need to do is do the masking like is done on the lm3208:17
shorneor maybe just change this...08:19
shorne    ret = cpu_openrisc_get_phys_addr(cpu, &physical, &prot,08:20
shorne                                     address, rw);08:20
shorneret = cpu_openrisc_get_phys_addr(cpu, &physical, &prot,08:20
shorne    address & 0x7fffffff, rw);08:20
shorneWhy do you want to do this?08:20
mithroshorne: I want qemu to emulate the behaviour of our hardware - our hardware does this08:22
shorneI guess do you dont cache io (which changes without cpu knowledge)08:22
mithroI mean I have it working by mapping my io emulation at the 0x80000000-0xffffffff ranges08:26
mithroI'm just trying to make it so that  0x00000000-0x7fffffff and 0x80000000-0xffffffff are mapped to the same memory region08:26
mithroI'm also worried about the possibility of data caching....08:27
shornedoing the change I mentioned would effectively do that, at least when mmu is on08:28
shornethey will map to the same region, I am not sure of the caching, maybe qemu doesnt really do caching08:29
shorneyou can ask in #qemu on OFTC08:29
shorneI need to be away08:30
mithroshorne: thanks08:37
shornestekern_: I found some old conversation from you about dsx in mor1kx10:17
shornethe spec is a bit strange around this...10:19
shorneSR[DSX] - 1 if EPCR is delay slot (after exception)10:20
shorneESR <- set to SR after excption10:21
shorneIf we do rfe, does SR[DSX] reset?  it looks like not in the verilog10:23
shorneI think i broke linux and qemu related to this :(10:23
shorneI made them to check ESR[DSX] for the ECPR in delay slot10:26
shornethey should check SR[DSX] (i guess)10:26
shorneAnyone know how to override defines in fusesoc quartus build?12:52
shornei.e like iverilog_options=-DSIM12:53
shorneI want to do for quartus...12:53
shornethere is a sub module (
shorneneed to define DBG_CPU1_SUPPORTED12:53
shorneI looked through code and quartus build scripts, it didnt seem possible12:54
--- Log closed Sat Apr 01 00:00:09 2017

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