| --- Log opened Fri Mar 31 00:00:08 2017 | ||
| mithro | Is the mor1k and or1200 instruction set the same? | 04:34 |
|---|---|---|
| mithro | Anyone here understand the mmu emulation stuff in qemu? | 05:36 |
| bandvig | mithro: (1) mor1kx and or1200 are just different implementation of the same architecture, so, ISA is also same for them. (2) Could not say nanything related MMU in QEMU. | 06:38 |
| mithro | bandvig: thanks, that is what I thought but wanted to check.. | 07:01 |
| shorne_ | mithro: I know a bit about mmu qemu, I have some patches waiting for next qemu merge cycle | 07:47 |
| shorne_ | https://github.com/stffrdhrn/qemu/commit/93f7ef78432ebaa2ca6dc961b3f32df7bf94729d | 07:47 |
| shorne_ | but really I just know the openrisc implementation, not general qemu much | 07:47 |
| -!- shorne_ is now known as shorne | 07:48 | |
| mithro | shorne: On the lm32 we have the ability for the processor to ignore the MSB, with reads that go to the upper half bypassing the cache | 07:49 |
| mithro | shorne: I'm trying to understand how I can add that to the openrisc emulation | 07:50 |
| shorne | let me have a look at lm32... | 07:52 |
| shorne | cpu_lm32_set_phys_msb_ignore(env, 1);? | 07:53 |
| shorne | it seems that all lm32 does differnt when that is set is mask the hwaddress sent to tlb_set_page() | 08:00 |
| shorne | tlb_set_page(cs, address, address & 0x7fffffff, prot, mmu_idx, ... | 08:00 |
| mithro | shorne: I don't necessarily understand everything yet :-P | 08:03 |
| mithro | shorne: As far as I understand though, if you access the values from one region you end up reading through the CPU's cache, if you access it from another you read it directly -- maybe in QEmu there is no emulation of the caching behaviour? | 08:04 |
| mithro | The README in the target-lm32 says | 08:06 |
| mithro | Some SoC ignores the MSB on the address bus. Thus creating a shadow memory area. As a general rule, 0x00000000-0x7fffffff is cached, whereas 0x80000000-0xffffffff is not cached and used to access IO devices. | 08:06 |
| mithro | shorne: Doesn't look like the lm32 CPU has any icache/dcache emulation that I can see? | 08:11 |
| shorne | right, I dont know too much about it allso, but what I see is this method is part of qemu core | 08:12 |
| shorne | tlb_set_page() | 08:12 |
| shorne | its for setting the qemu internal TLB (maybe thats what you mean by cache) | 08:12 |
| shorne | for lm32 it doesnt look like there is really man mmu | 08:12 |
| shorne | so the address requested, is simply added to the tlb | 08:13 |
| shorne | tlb_set_page ((virtual)addr, (physical)addr) | 08:13 |
| shorne | or if the msb ignore thing is set it does | 08:13 |
| shorne | tlb_set_page ((virtual) addr, (physical)addr &07ffffffff) | 08:14 |
| shorne | It dont see how that means its "ignored" really | 08:14 |
| shorne | but for openrisc with a mmu it doesn | 08:14 |
| shorne | cpu_openrisc_get_phys_addr((virtual)addr, &physical) | 08:15 |
| shorne | if (that worked) | 08:15 |
| shorne | tlb_set_page ((virtual)addr, physical & PAGE_MASK) | 08:16 |
| mithro | https://github.com/m-labs/misoc/blob/master/misoc/cores/mor1kx/core.py#L26 -- Looks like we get the shadowing via setting the OPTION_DCACHE_LIMIT_WIDTH to 31 bits in the FPGA | 08:16 |
| shorne | right, so I think all you would need to do is do the masking like is done on the lm32 | 08:17 |
| shorne | or maybe just change this... | 08:19 |
| shorne | ret = cpu_openrisc_get_phys_addr(cpu, &physical, &prot, | 08:20 |
| shorne | address, rw); | 08:20 |
| shorne | to | 08:20 |
| shorne | ret = cpu_openrisc_get_phys_addr(cpu, &physical, &prot, | 08:20 |
| shorne | address & 0x7fffffff, rw); | 08:20 |
| shorne | Why do you want to do this? | 08:20 |
| mithro | shorne: I want qemu to emulate the behaviour of our hardware - our hardware does this | 08:22 |
| shorne | I guess do you dont cache io (which changes without cpu knowledge) | 08:22 |
| mithro | Yeah | 08:25 |
| mithro | I mean I have it working by mapping my io emulation at the 0x80000000-0xffffffff ranges | 08:26 |
| mithro | I'm just trying to make it so that 0x00000000-0x7fffffff and 0x80000000-0xffffffff are mapped to the same memory region | 08:26 |
| mithro | I'm also worried about the possibility of data caching.... | 08:27 |
| shorne | doing the change I mentioned would effectively do that, at least when mmu is on | 08:28 |
| shorne | they will map to the same region, I am not sure of the caching, maybe qemu doesnt really do caching | 08:29 |
| shorne | you can ask in #qemu on OFTC | 08:29 |
| shorne | I need to be away | 08:30 |
| mithro | shorne: thanks | 08:37 |
| shorne | stekern_: I found some old conversation from you about dsx in mor1kx | 10:17 |
| shorne | http://juliusbaxter.net/openrisc-irc/%23openrisc.2012-11-28.log.html | 10:17 |
| shorne | the spec is a bit strange around this... | 10:19 |
| shorne | SR[DSX] - 1 if EPCR is delay slot (after exception) | 10:20 |
| shorne | ESR <- set to SR after excption | 10:21 |
| shorne | If we do rfe, does SR[DSX] reset? it looks like not in the verilog | 10:23 |
| shorne | I think i broke linux and qemu related to this :( | 10:23 |
| shorne | I made them to check ESR[DSX] for the ECPR in delay slot | 10:26 |
| shorne | they should check SR[DSX] (i guess) | 10:26 |
| shorne | Anyone know how to override defines in fusesoc quartus build? | 12:52 |
| shorne | i.e like iverilog_options=-DSIM | 12:53 |
| shorne | I want to do for quartus... | 12:53 |
| shorne | there is a sub module (https://github.com/olofk/adv_debug_sys/blob/master/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v) | 12:53 |
| shorne | need to define DBG_CPU1_SUPPORTED | 12:53 |
| shorne | I looked through code and quartus build scripts, it didnt seem possible | 12:54 |
| --- Log closed Sat Apr 01 00:00:09 2017 | ||
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