IRC logs for #openrisc Tuesday, 2017-01-10

--- Log opened Tue Jan 10 00:00:07 2017
stekernshorne: to help me context switch into what you are speaking about, can you post a link to the code you're referring to?01:56
shorneexample for Jesper and others who want to build a page allocator for02:32
shornein traps.c line 34702:33
shorneIgnore my first line, Im on phone, paste not working so well02:33
shorneSorry, line 34202:34
-!- Netsplit *.net <-> *.split quits: eliask, killertux04:38
-!- Netsplit over, joins: killertux04:39
stekernshorne: I agree, but it's going to be painful...06:19
shornestekern: how painful I can think of a few things06:48
shorne1. need to check the status of 'flag' at the time of exception to properly do, l.bnf06:48
stekernunconditional jumps should be pretty straightforward I suppose. conditional ones, more painful06:48
shorne2. need to update r9 in case of l.jal / l.jalr (asuming its not updated)06:49
shorneI think the flag we can get pretty easy from ESR[f]06:49
stekernmaybe it's not *that* painful after all06:50
stekernbut you have to emulate quite a bit06:50
stekernsoon you have a whole or1k emulator within the kernel ;)06:50
shorneYeah, there might be some cases I am not thinking of, at least there is not immediate arithmatic in the Jump instructions like l.j 5(r3)06:51
shorneAnyway, like I was saying I was researching a bit, it seems other architectures like microblaze have a BTR (branch target register).   It stored the next PC in the case that the exception occurred in delay slot06:52
shorneand l.rfe will always use that instead of EPC.06:53
shorneI'll work on the patch, I think after that the whole patch set should be looking good to me06:53
shorneFYI, this is the set right now:
shornestekern: check it out
shorneI implemented it, need to test it09:45
shorneit builds09:45
shornecool, qemu doesnt have the instruction, but it crashes11:11
shornesorry, thought I lost connection11:13
shorneI mean, qemu runnin the kernel gets into do_illegal_instruction, but the goes to die11:14
shorneso, its something I can debug11:14
shornemaking progress11:14
stekernshorne: I've only tested the emulation code with or1k with the instructions disabled11:57
shornestekern: I see, it might be my code causing the failure, still tracing where its going wrong12:12
shornehmm, maybe bug in qemu, the instruction loaded in the emulator is not the one that caused the illegal instruction, instead its the first instruction in the 'function' that caused the illegal instruction12:24
shornelooks wrong12:24
shorneit pulls the right address from EPCR12:28
shornebut EEAR does not load the instruction address12:35
shorneit loads something else12:35
shornehmm, patch qemu? or just do or1ksim12:36
shornetime for bed, so seems a but in qemu around handling illegal instructions , does not set EEAR correctly (expected to get PC for error instruction, instead got something else)12:37
shornea bug12:38
--- Log closed Wed Jan 11 00:00:08 2017

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