IRC logs for #openrisc Sunday, 2016-12-25

--- Log opened Sun Dec 25 00:00:43 2016
andrzejrolofk, I don't think you will be able to saturate ui bus with wb without multi-port access (like in atlys) or some clever caching in the bridge.07:44
andrzejrbtw, my bridge with read and write bursts mostly works. I was having some issues with the linux kernel hanging and I never figured out if that was due to an obscure bug in the bridge or somewhere else. I haven't looked into it for over a year now.07:47
Findewe have a fairly simple ui bridge in openpiton07:50
Findenot from wb, but from our own noc protocol07:50
olofkandrzejr, Finde: I have two dedicated UI ports on the memory controller for doing large burst reads and writes. They are connected to a DMA streamer, so there's no wb involved there. I just need two extra ports for the I/D bus of the openrisc, and those don't need to be high performance17:50
andrzejrolofk, if you feel brave enough my code may just work for you.
andrzejrused it with
andrzejrnote that the following line currently disables bursts:
olofkThanks. I'll give it a try. Likely, I'll survive without burst17:59
andrzejrburts may still work for you (like they did for me), I don't know what was causing the system instability, could be many other reasons. Let me know if you find anything.18:04
andrzejrolofk, here is a bfm of the ui bus I used, probably totally wrong but still useful for some quick simulations:
olofkThanks. That could be useful too for doing simulations without bringing in the real memory controller18:12
--- Log closed Mon Dec 26 00:00:44 2016

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