| --- Log opened Sun Dec 25 00:00:43 2016 | ||
| andrzejr | olofk, I don't think you will be able to saturate ui bus with wb without multi-port access (like in atlys) or some clever caching in the bridge. | 07:44 |
|---|---|---|
| andrzejr | btw, my bridge with read and write bursts mostly works. I was having some issues with the linux kernel hanging and I never figured out if that was due to an obscure bug in the bridge or somewhere else. I haven't looked into it for over a year now. | 07:47 |
| Finde | we have a fairly simple ui bridge in openpiton | 07:50 |
| Finde | not from wb, but from our own noc protocol | 07:50 |
| olofk | andrzejr, Finde: I have two dedicated UI ports on the memory controller for doing large burst reads and writes. They are connected to a DMA streamer, so there's no wb involved there. I just need two extra ports for the I/D bus of the openrisc, and those don't need to be high performance | 17:50 |
| andrzejr | olofk, if you feel brave enough my code may just work for you. https://github.com/andrzej-r/orpsoc-cores/tree/nexys4ddr/systems/nexys4ddr/nexys4ddr_ddr2_wb | 17:56 |
| andrzejr | used it with https://github.com/andrzej-r/orpsoc-cores/tree/nexys4ddr/systems/nexys4ddr/nexys4ddr_ddr2 | 17:56 |
| andrzejr | note that the following line currently disables bursts: https://github.com/andrzej-r/orpsoc-cores/blob/nexys4ddr/systems/nexys4ddr/nexys4ddr_ddr2_wb/rtl/nexys4ddr_ddr2_wb_to_ui.v#L109 | 17:58 |
| olofk | Thanks. I'll give it a try. Likely, I'll survive without burst | 17:59 |
| andrzejr | burts may still work for you (like they did for me), I don't know what was causing the system instability, could be many other reasons. Let me know if you find anything. | 18:04 |
| andrzejr | olofk, here is a bfm of the ui bus I used, probably totally wrong but still useful for some quick simulations: https://github.com/andrzej-r/orpsoc-cores/tree/nexys4ddr/systems/nexys4ddr/nexys4ddr_ddr2_bfm | 18:10 |
| olofk | Thanks. That could be useful too for doing simulations without bringing in the real memory controller | 18:12 |
| --- Log closed Mon Dec 26 00:00:44 2016 | ||
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