| --- Log opened Sun Nov 06 00:00:30 2016 | ||
| shorne_ | wbx: I didnt set any option to enable those instructions, and I am not saying those are part of the fix. Just those are the instructions it is failing at for me. | 04:15 |
|---|---|---|
| shorne_ | Could you post your objdump of busybox again? | 04:15 |
| -!- shorne_ is now known as shorne | 04:15 | |
| wbx | shorne: http://debug.openadk.org/or1k/busybox.or1k.2 | 05:09 |
| wbx | shorne: i was just wondering why I get other results than you. | 05:10 |
| kc5tja | Anyone have experience debugging why iverilog would simply ... stop ... after 300 or so clock ticks? | 13:34 |
| ZipCPU | kc5tja: You got your answer on the #riscv channel, right? | 14:54 |
| kc5tja | No. | 15:38 |
| olofk | kc5tja: You can run Icarus in interactive mode and single-step. Might help | 16:33 |
| kc5tja | It does nothing. :( | 16:42 |
| kc5tja | It still just ..... stops dead. | 16:43 |
| kc5tja | There's _no_ rational reason why the clock should just stop. | 16:43 |
| kc5tja | strace shows no activity taken by vvp once it reaches this point. | 16:44 |
| kc5tja | top shows vvp is consuming 100% CPU. | 16:44 |
| kc5tja | Other than that, it's completely baffling. I just don't know what to do anymore. | 16:44 |
| olofk | kc5tja: Are you loading some big memory file or something at that point? | 16:50 |
| olofk | Is it coupled to releasing reset? | 16:50 |
| olofk | Any particular event going on at that time? | 16:50 |
| olofk | Have you tried other simulators? | 16:52 |
| olofk | Is it polaris you're running? The stuff that's checked in on github? | 16:52 |
| kc5tja | Coupled to releasing reset? <-- not sure what you're asking here. Reset is explicitly managed in the top-level, so nothing else controls it. | 16:54 |
| kc5tja | event at that time? <-- Yes, I'm trying to $display() a character that the computer is trying to write to a CSR. | 16:55 |
| kc5tja | other simulators? <-- No. While the thought has crossed my mind, going into ISE is just heavyweight. | 16:55 |
| kc5tja | Polaris? <-- Yes. | 16:55 |
| kc5tja | Github? <-- Yes. | 16:55 |
| kc5tja | Specifically, the code in docs/example | 16:56 |
| olofk | Can't find docs/example | 16:56 |
| olofk | Which testbench are you running? PolarisCPU_tb? | 16:58 |
| kc5tja | No | 16:58 |
| kc5tja | https://github.com/sam-falvo/polaris | 16:58 |
| olofk | oh... I used the one from KestrelComputer | 16:59 |
| olofk | Ok, so you run run.sh from there, right? | 17:01 |
| olofk | from docs/example | 17:01 |
| kc5tja | Yeah, I just found a few bugs though. charByte_mux needs to be an 8-bit wide wire; it's defined as a single-bit wire. | 17:05 |
| kc5tja | It's something to do with the csrrw instruction. | 17:07 |
| kc5tja | When I change the program to use csrrs instruction instead (and adjust the output.v start and stop bit conditions to match), it works fine. | 17:07 |
| kc5tja | But, I'm just totally baffled why csrrw would cause this problem. | 17:07 |
| olofk | Works in modelsim after I fixed a couple of syntax problems | 17:15 |
| kc5tja | Did it print out a bunch of "A"s to the screen? | 17:15 |
| olofk | Hard to say. Lots of debug stuff being printed | 17:16 |
| olofk | Removed the monitor line now | 17:16 |
| olofk | Nothing is showing up so far | 17:17 |
| kc5tja | OK, so it's not working then. | 17:17 |
| olofk | You got a bunch of missing connections, in case you didn't know | 17:17 |
| olofk | At least it comes further in modelsim than in icarus | 17:17 |
| kc5tja | A lot of outputs are left unconnected, yes. All inputs should be connected. | 17:17 |
| olofk | in icarus, I got stuck at tim 1280 | 17:17 |
| kc5tja | Yep, that's where I get stuck too. | 17:18 |
| kc5tja | Although I got mine to print a single "A" before it dies, so I know it hits $display before it fails completely. | 17:18 |
| kc5tja | I'm going to try changing csrrw so that reads and writes happen on different cycles. | 17:20 |
| kc5tja | This will completely break the existing test benches, but let's see if this helps. | 17:20 |
| olofk | Looks like you at least got a clue where the problem might be | 17:20 |
| olofk | Got to run. Good luck | 17:21 |
| kc5tja | Nope, that didn't fix it. So I know it's not that. | 17:24 |
| kc5tja | Finally got around to trying it with ISE, and it simulates just fine. | 20:00 |
| kc5tja | ZipCPU: yt? | 20:16 |
| ZipCPU | kc5tja: Just got back to the keyboard. Wu? | 20:24 |
| ZipCPU | kc5tja: Is it possible that you have a logic loop? | 20:34 |
| ZipCPU | Do you have simulations that last and run longer than the failing one is supposed to run? | 20:34 |
| ZipCPU | kc5tja: Check this out ... http://stackoverflow.com/questions/10528457/debugging-combinational-logic-loops-in-icarus-verilog | 20:50 |
| kc5tja | Gah, we keep missing each other. | 22:21 |
| --- Log closed Mon Nov 07 00:00:31 2016 | ||
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