IRC logs for #openrisc Sunday, 2016-11-06

--- Log opened Sun Nov 06 00:00:30 2016
shorne_wbx: I didnt set any option to enable those instructions, and I am not saying those are part of the fix.  Just those are the instructions it is failing at for me.04:15
shorne_Could you post your objdump of busybox again?04:15
-!- shorne_ is now known as shorne04:15
wbxshorne: i was just wondering why I get other results than you.05:10
kc5tjaAnyone have experience debugging why iverilog would simply ... stop ... after 300 or so clock ticks?13:34
ZipCPUkc5tja: You got your answer on the #riscv channel, right?14:54
olofkkc5tja: You can run Icarus in interactive mode and single-step. Might help16:33
kc5tjaIt does nothing.  :(16:42
kc5tjaIt still just ..... stops dead.16:43
kc5tjaThere's _no_ rational reason why the clock should just stop.16:43
kc5tjastrace shows no activity taken by vvp once it reaches this point.16:44
kc5tjatop shows vvp is consuming 100% CPU.16:44
kc5tjaOther than that, it's completely baffling.  I just don't know what to do anymore.16:44
olofkkc5tja: Are you loading some big memory file or something at that point?16:50
olofkIs it coupled to releasing reset?16:50
olofkAny particular event going on at that time?16:50
olofkHave you tried other simulators?16:52
olofkIs it polaris you're running? The stuff that's checked in on github?16:52
kc5tjaCoupled to releasing reset?  <-- not sure what you're asking here.  Reset is explicitly managed in the top-level, so nothing else controls it.16:54
kc5tjaevent at that time? <-- Yes, I'm trying to $display() a character that the computer is trying to write to a CSR.16:55
kc5tjaother simulators? <-- No.  While the thought has crossed my mind, going into ISE is just heavyweight.16:55
kc5tjaPolaris? <-- Yes.16:55
kc5tjaGithub? <-- Yes.16:55
kc5tjaSpecifically, the code in docs/example16:56
olofkCan't find docs/example16:56
olofkWhich testbench are you running? PolarisCPU_tb?16:58
olofkoh... I used the one from KestrelComputer16:59
olofkOk, so you run from there, right?17:01
olofkfrom docs/example17:01
kc5tjaYeah, I just found a few bugs though.  charByte_mux needs to be an 8-bit wide wire; it's defined as a single-bit wire.17:05
kc5tjaIt's something to do with the csrrw instruction.17:07
kc5tjaWhen I change the program to use csrrs instruction instead (and adjust the output.v start and stop bit conditions to match), it works fine.17:07
kc5tjaBut, I'm just totally baffled why csrrw would cause this problem.17:07
olofkWorks in modelsim after I fixed a couple of syntax problems17:15
kc5tjaDid it print out a bunch of "A"s to the screen?17:15
olofkHard to say. Lots of debug stuff being printed17:16
olofkRemoved the monitor line now17:16
olofkNothing is showing up so far17:17
kc5tjaOK, so it's not working then.17:17
olofkYou got a bunch of missing connections, in case you didn't know17:17
olofkAt least it comes further in modelsim than in icarus17:17
kc5tjaA lot of outputs are left unconnected, yes.  All inputs should be connected.17:17
olofkin icarus, I got stuck at tim 128017:17
kc5tjaYep, that's where I get stuck too.17:18
kc5tjaAlthough I got mine to print a single "A" before it dies, so I know it hits $display before it fails completely.17:18
kc5tjaI'm going to try changing csrrw so that reads and writes happen on different cycles.17:20
kc5tjaThis will completely break the existing test benches, but let's see if this helps.17:20
olofkLooks like you at least got a clue where the problem might be17:20
olofkGot to run. Good luck17:21
kc5tjaNope, that didn't fix it.  So I know it's not that.17:24
kc5tjaFinally got around to trying it with ISE, and it simulates just fine.20:00
kc5tjaZipCPU: yt?20:16
ZipCPUkc5tja: Just got back to the keyboard.  Wu?20:24
ZipCPUkc5tja: Is it possible that you have a logic loop?20:34
ZipCPUDo you have simulations that last and run longer than the failing one is supposed to run?20:34
ZipCPUkc5tja: Check this out ...
kc5tjaGah, we keep missing each other.22:21
--- Log closed Mon Nov 07 00:00:31 2016

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