IRC logs for #openrisc Tuesday, 2016-10-11

--- Log opened Tue Oct 11 00:00:51 2016
_franck__^ ELCE talk04:28
olofkI should get him to use FuseSoC :)04:39
-!- Netsplit *.net <-> *.split quits: Shentino, SMDhome1, LoneTech, Amadiro_, Finde, Hoolootwo, _florent_, parasite04:41
-!- Netsplit over, joins: Shentino04:48
olofkIs anyone going to ELCE?04:53
olofkoh, it's now04:55
wallentoZipCPU, you there?07:33
ZipCPUGood morning, wallento!07:49
wallentogood morning, I have a question regarding your talk07:50
wallentowanted to catch you, but time was running so fast this weekend07:50
ZipCPUSure, I love questions!07:50
wallentoThe 32 bits loads and stores only, first striked me a bit of a mood-killer07:51
wallentobut then my thoughts diverged from your actual presentation07:51
ZipCPUGo on ...07:51
wallentoI was thinking: "Okay, 32 bits accesses only, but you can still map reading uint8_t to a 32 bit aligned load and AND or shift left 24-shift right 24"07:52
wallentobut you said there is no uint8_t supported07:52
wallentois that because you cannot do what I was thinking efficiently?07:52
ZipCPUYeah ... so, here's the problem: The ZipCPU supports 32-bit addressing, where each address # references a word of memory.07:53
ZipCPUWhile I could create Load/Store instructions with the lower bits of the address, and have the compiler automatically adjust to get a character of interest,07:53
ZipCPUI'd then need a 30 bit address instead of a 32-bit address.07:54
ZipCPUThe alternative, would be to move to 34-bit addresses for everything ... but that would require two words of storage.07:54
ZipCPUI should point out ... I may yet be convinced to add the LB, SB, LH, and SH instructions.  There's room in the instruction set for them (I'd steal it from the unused FPU instructions ...).  I'm really on the fence on this issue.  I keep going back and forth.07:56
ZipCPUIt would mean a lot of rework with GCC and binutils ... but it's all doable.07:56
ZipCPUI think they'd both be happier with byte-wise access.07:57
ZipCPUI should point out ... the rest of the world uses the 30-bit address solution ... allowing you to address 4GB of memory.08:02
ZipCPUZipCPU is unusually with its 32-word address solution, allowing access to 16GB of memory, 4bytes at a time.08:02
wallentommh, I am still not sure08:05
wallentoactually I am08:06
wallento30 bit addresses are okay, right08:06
wallentoyou could still use 32 bit addresses, but use word adressing08:06
wallentoand teach the compiler/binutils that an unaligned load is a sequence of instructions08:07
wallentosb of 0x1 is load from 0x0, shift right by eight and mask upper 2408:08
wallentothe thing is, that's exactly what the bus interface does08:08
wallentoin other cpus08:08
ZipCPUYes.  If I were to create SB,LB,SH, and LH instructions ... that's exactly what I'd need to do.08:09
ZipCPUI already have something similar in the wb2axip core--it dynamically converts a 32-bit data bus to a 128-bit data bus, in much of the same way.08:10
wallentocode density becomes a serious issue than08:11
ZipCPUHow so?08:13
ZipCPUDo you mean ... if the CPU needs to issue instructions to shift words around?08:14
ZipCPUI think, if I adjusted the bus for 30+2 bit support, adding the automatic shifts into the hardware would be the least of my worries.08:14
ZipCPUSupport would also need to add "instructions" (really just RTL to instruction sequences) for using 8-bit an 16-bit numbers as well.  This would probably (primarily) consist of instructions to (un)sign extend 8-bit/16-bit words to 32-bit words.08:18
wallentoyeah, I mean that08:22
ZipCPUwallento: If the ZipCPU had 8-bit access, would you be more interested in trying it out?11:33
wallentoI am interested in trying it out anyways11:34
wallentoas I said I also like the idea of the 32-bit access11:35
wallentobut you buy it with a lot of disadvantages I think11:35
wallentogiven the design complexity, it would be worth comparing both11:35
ZipCPUThanks!  I'll keep it as is then, for now, but let me know how ... experience ... goes, and (please) let me know if you have any troubles.11:39
-!- Finde_ is now known as Finde11:46
kc5tjaDEC Alpha was a word-only load/store architecture, and it suffered because of it.  Too many programs (at least those written in C) relied on byte or half-word sized units of data.11:47
kc5tjaThey eventually added sub-word accessors to the instruction set, as I recall.11:48
kc5tjaI don't know how they managed addressing using the lower bits though.11:48
wallentothings get messy when your write to the word is not exclusive12:05
wallentolike two processors using uin8_t in the same word12:05
SMDnoteWe need to change openrisc isa in orvdx part: at least we need to fix opcodes encoding14:12
SMDnotehow should I propose that changes?14:12
olofkSMDnote: Bring it to the mailing list for discussion14:50
SMDnoteolofk: could you tell to which mailing list I should write?14:53
olofkor if you're already registered15:00
SMDnoteolofk: thanks15:05
SMDnoteolofk: I think I've sent it15:34
olofkSMDnote: Yes you did. I will take a closer look, but I got an awful lot to do so it will have to wait15:50
--- Log closed Wed Oct 12 00:00:53 2016

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