| --- Log opened Wed Oct 05 00:00:42 2016 | ||
| olofk | Looks like Adapteva has taped-out the Epiphany V now | 03:04 |
|---|---|---|
| _franck__ | A guide for anyone here: http://fr.slideshare.net/coudot/kr2016-the-free-software-bastard-guide :) | 03:33 |
| olofk | _franck_: Oh, I'm totally an asshole developer :) | 04:15 |
| olofk | Think that every one of those statements applied to me | 04:16 |
| olofk | Don't know how many times I have pointed people asking for documentation to some mailing list archive post or a long reply to a bug report :) | 04:16 |
| olofk | So....SORRY everyone | 04:16 |
| olofk | Just wrote a reply to an article that was about as long as the article itself :) http://www.eejournal.com/archives/articles/20161004-opensource/ | 04:23 |
| _franck__ | olofk: sorry if that slide make you face the reality :) I attended the conference and the speaker was so funny. Best quote is "TEST IS DOUBT". I'll remember this one. | 04:29 |
| _franck__ | I don't think long answer are bad. I'll read yours | 04:29 |
| shorne | olofk: we hesitate to start documents because it requirest structure. which we already do in our programs | 06:00 |
| shorne | doing again and thinking of what our audience needs to know is a lot of work | 06:01 |
| shorne | but just answering questions is easy :) | 06:01 |
| shorne | I read your answer on FPGA tools and its good | 06:01 |
| shorne | I thought my flight leaves tomorrow afternoon, but its tonight in 5 hours! | 06:02 |
| shorne | need to rush! | 06:02 |
| stekern | better to find out that now than tomorrow afternoon though ;) | 06:03 |
| shorne | yeah, tell me about it, luckily google now alerted me saying "weather in bologna"... | 06:05 |
| shorne | I thought, why is it telling me about weater... then ope to find "flight in 6 hours"... | 06:05 |
| olofk | shorne: Have a safe flight and see you soon | 06:35 |
| shorne | thanks see you all soon | 06:49 |
| olofk | Huh... I had no idea about the verilog 'config' keyword | 09:05 |
| olofk | Apparently it's possible to use libraries in Verilog. One of the top features I've been missing from VHDL | 09:06 |
| olofk | Unfortunately it seems to be mostly unusable from a quick read | 09:06 |
| olofk | Since you need to specify in the source code (what??) the path to the library source code | 09:06 |
| olofk | oh.. might might be wrong on that point | 09:07 |
| olofk | I'll take a closer look another day. I came across it when I saw that yosys listed it as not supported | 09:23 |
| olofk | So it would probably not be portable across tools anyway | 09:23 |
| -!- Netsplit *.net <-> *.split quits: fotis2, bentley`, doomlord, parasite | 10:39 | |
| -!- Netsplit over, joins: parasite | 10:39 | |
| -!- Netsplit over, joins: fotis2 | 10:40 | |
| --- Log closed Thu Oct 06 00:00:44 2016 | ||
Generated by irclog2html.py 2.15.2 by Marius Gedminas - find it at mg.pov.lt!