| --- Log opened Tue Sep 20 00:00:20 2016 | ||
| olofk | Good. I'll make myself an inofficial wishbone variant then | 02:05 |
|---|---|---|
| olofk | stekern: Caches are off after reset, right? Is there a different behaviour with them on/off? | 02:16 |
| olofk | Or is that MicroBlaze I'm thinking of? :) | 02:17 |
| stekern | olofk: different behaviour in what sense? bus accesses? | 05:44 |
| stekern | all accesses are single when the caches are off | 05:44 |
| stekern | and yes, they are off after reset | 05:45 |
| olofk | stekern: Yes, that was what I was thinking about. So I can't hardcode it outside of mor1kx, but need to hook up something internally to check if caches are on | 06:31 |
| stekern | what exactly are you doing? | 06:32 |
| stekern | you can probably hook up to the internal bus logic of mor1kx | 06:33 |
| stekern | it has a 'burst' indication signal | 06:33 |
| olofk | I need to talk to a Avalon DDR2 controller from Quartus | 06:34 |
| olofk | Was using wb_altera_ddr_wrapper (which is basically wb_sdram_ctrl with a avalon if instead of and SDRAM IF), but all the latency kills my bandwidth | 06:35 |
| olofk | So now I'm thinking of just using a dumb arbiter with an avalon if towards the memory | 06:35 |
| olofk | But for that I need to know the burst length so I can set that on the avalon side | 06:35 |
| olofk | I got mor1kx dbus and ibus + a DMA streamer as masters | 06:36 |
| stekern | I had some related hacks related to the same type of problem in the wb to avalon bridge | 06:36 |
| olofk | The one I removed from mor1kx? | 06:37 |
| stekern | no | 06:37 |
| stekern | the one in orpsoc-cores | 06:37 |
| stekern | or is it fusesoc-cores now | 06:37 |
| stekern | https://github.com/openrisc/orpsoc-cores/tree/master/cores/wb_avalon_bridge | 06:39 |
| stekern | that | 06:39 |
| olofk | cool. I see it now | 06:40 |
| olofk | Does it work? :) | 06:40 |
| stekern | ...so, I opted to not use the bursts but pipelined accesses | 06:41 |
| stekern | yes, I've been using it *a lot* on sockit | 06:41 |
| olofk | aha | 06:41 |
| stekern | to talk to a avalon ddr2(3?) controller from Quartus | 06:41 |
| olofk | I'll take a look at the sockit code | 06:42 |
| olofk | Do you have multiple memory masters? | 06:42 |
| olofk | And are they all wb or avalon? | 06:42 |
| stekern | umm, yes...I think ;) | 06:43 |
| stekern | I can't remember exactly how I hooked things up | 06:44 |
| olofk | After a quick look it looks like the arbiter is likely generated in the hps (with qsys?) | 06:45 |
| stekern | ah, yes | 06:46 |
| olofk | I thought of the possibility to add a Quartus avalon arbiter, but the thought of having to use qsys just for that makes me want to kill myself | 06:52 |
| olofk | I'll try a wishbone arbiter and just the bridge to begin with | 06:54 |
| olofk | Oh great. Do they use different dialects of Avalon? | 07:00 |
| olofk | I hate that bus | 07:01 |
| olofk | Oh no! I need a cdc too | 07:02 |
| olofk | A | 07:10 |
| olofk | Thought I could reuse the sockit qsys, but now I see that the mem controller in there support multiple ports natively | 07:11 |
| olofk | While the one for Cyclone IV only support the older architecture with one port | 07:11 |
| stekern | aha | 07:12 |
| stekern | yes, that's why I was confused by your question about multiple memory masters | 07:12 |
| olofk | stekern: Is waitrequest and ready the same signal? | 07:18 |
| stekern | maybe, it was a while since I looked at the avalon spec | 07:19 |
| stekern | but I remember that there was signals that were called different things but seemed to mean the same thing | 07:20 |
| shorne | wallento: I am working on writing a quick not to Matjaz, is there anything you want to mention? | 07:22 |
| olofk | avalon is so messy | 07:25 |
| wallento | I opencores.org officially dead now? | 09:20 |
| wallento | \o/ | 09:20 |
| ZipCPU | I'm not getting any response from their server. | 09:22 |
| olofk | Naahh... it's probably just down as usual | 09:22 |
| ZipCPU | Yeah ... probably. | 09:22 |
| ZipCPU | It was up last night. | 09:23 |
| ZipCPU | And, as I recall, even earlier this morning. | 09:23 |
| wallento | lets hope it does not have to suffer much longer | 09:24 |
| -!- hammond-ey is now known as hammond | 11:29 | |
| olofk | We have transferred all the interesting OpenRISC stuff from OpenCores already, right? | 15:51 |
| olofk | Like the wiki | 15:51 |
| shorne | stekern: what is the process for updating the openrisc spec? I saw the last changes were done by you on opencores. Is there any formal process? | 16:59 |
| shorne | wallento: Also, is there any issue with us putting redirect links on the opencores pages to our github and openrisc.io pages? | 17:00 |
| shorne | stekern: about the spec changes I found this https://github.com/openrisc/doc/tree/arch-1.2-proposal | 18:17 |
| shorne | I guess we need a page on openrisc.io about the process, Ill send a proposal for a spec update to reserve r10 for TLS | 18:19 |
| stekern | shorne: the process has previously been that we gather suggestions, then we discuss them and decide which should be accepted into the next revision of the spec | 23:05 |
| --- Log closed Wed Sep 21 00:00:21 2016 | ||
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