IRC logs for #openrisc Tuesday, 2016-09-20

--- Log opened Tue Sep 20 00:00:20 2016
olofkGood. I'll make myself an inofficial wishbone variant then02:05
olofkstekern: Caches are off after reset, right? Is there a different behaviour with them on/off?02:16
olofkOr is that MicroBlaze I'm thinking of? :)02:17
stekernolofk: different behaviour in what sense? bus accesses?05:44
stekernall accesses are single when the caches are off05:44
stekernand yes, they are off after reset05:45
olofkstekern: Yes, that was what I was thinking about. So I can't hardcode it outside of mor1kx, but need to hook up something internally to check if caches are on06:31
stekernwhat exactly are you doing?06:32
stekernyou can probably hook up to the internal bus logic of mor1kx06:33
stekernit has a 'burst' indication signal06:33
olofkI need to talk to a Avalon DDR2 controller from Quartus06:34
olofkWas using wb_altera_ddr_wrapper (which is basically wb_sdram_ctrl with a avalon if instead of and SDRAM IF), but all the latency kills my bandwidth06:35
olofkSo now I'm thinking of just using a dumb arbiter with an avalon if towards the memory06:35
olofkBut for that I need to know the burst length so I can set that on the avalon side06:35
olofkI got mor1kx dbus and ibus + a DMA streamer as masters06:36
stekernI had some related hacks related to the same type of problem in the wb to avalon bridge06:36
olofkThe one I removed from mor1kx?06:37
stekernthe one in orpsoc-cores06:37
stekernor is it fusesoc-cores now06:37
olofkcool. I see it now06:40
olofkDoes it work? :)06:40, I opted to not use the bursts but pipelined accesses06:41
stekernyes, I've been using it *a lot* on sockit06:41
stekernto talk to a avalon ddr2(3?) controller from Quartus06:41
olofkI'll take a look at the sockit code06:42
olofkDo you have multiple memory masters?06:42
olofkAnd are they all wb or avalon?06:42
stekernumm, yes...I think ;)06:43
stekernI can't remember exactly how I hooked things up06:44
olofkAfter a quick look it looks like the arbiter is likely generated in the hps (with qsys?)06:45
stekernah, yes06:46
olofkI thought of the possibility to add a Quartus avalon arbiter, but the thought of having to use qsys just for that makes me want to kill myself06:52
olofkI'll try a wishbone arbiter and just the bridge to begin with06:54
olofkOh great. Do they use different dialects of Avalon?07:00
olofkI hate that bus07:01
olofkOh no! I need a cdc too07:02
olofkThought I could reuse the sockit qsys, but now I see that the mem controller in there support multiple ports natively07:11
olofkWhile the one for Cyclone IV only support the older architecture with one port07:11
stekernyes, that's why I was confused by your question about multiple memory masters07:12
olofkstekern: Is waitrequest and ready the same signal?07:18
stekernmaybe, it was a while since I looked at the avalon spec07:19
stekernbut I remember that there was signals that were called different things but seemed to mean the same thing07:20
shornewallento: I am working on writing a quick not to Matjaz, is there anything you want to mention?07:22
olofkavalon is so messy07:25
wallentoI officially dead now?09:20
ZipCPUI'm not getting any response from their server.09:22
olofkNaahh... it's probably just down as usual09:22
ZipCPUYeah ... probably.09:22
ZipCPUIt was up last night.09:23
ZipCPUAnd, as I recall, even earlier this morning.09:23
wallentolets hope it does not have to suffer much longer09:24
-!- hammond-ey is now known as hammond11:29
olofkWe have transferred all the interesting OpenRISC stuff from OpenCores already, right?15:51
olofkLike the wiki15:51
shornestekern: what is the process for updating the openrisc spec?  I saw the last changes were done by you on opencores.  Is there any formal process?16:59
shornewallento: Also, is there any issue with us putting redirect links on the opencores pages to our github and pages?17:00
shornestekern: about the spec changes I found this
shorneI guess we need a page on about the process, Ill send a proposal for a spec update to reserve r10 for TLS18:19
stekernshorne: the process has previously been that we gather suggestions, then we discuss them and decide which should be accepted into the next revision of the spec23:05
--- Log closed Wed Sep 21 00:00:21 2016

Generated by 2.15.2 by Marius Gedminas - find it at!