IRC logs for #openrisc Saturday, 2016-08-27

--- Log opened Sat Aug 27 00:00:32 2016
--- Day changed Sat Aug 27 2016
-!- kc5tja_ is now known as kc5tja04:34
mor1kx[mor1kx] spacemonkeydelivers opened pull request #38: Introducing Performance Counter Unit (master...master)
SMDhome1Seems like I messed up w/ merging master to my fork and that's why I got lots of old commits in this pull request07:38
SMDhome1Let's just agree I don't know how to use git/github07:55
* ZipCPU mutters something unintelligible about the 16550 interface08:07
ZipCPUAnyone know where I can find and control the arguments given to Verilator?08:31
ZipCPUThat is ... from within fusesoc?08:32
SMDhome1try build/mor1kx-generic/sim-verilator/verilator.make.log08:35
ZipCPUStrange ... I don't have that file.08:35
SMDhome1but do you have build directory?08:36
ZipCPUYes, and a sim-verilator directory within it even.08:39
SMDhome1ZipCPU for it appears immidiately after running fusesoc --sim=verilator mor1kx-generic08:43
ZipCPUYou mean in the text that I can't read 'cause it's yellow on a white background?  ;)08:49
ZipCPUNo ... it's not there.08:50
ZipCPUFor some reason, the mor1kx-generic UART isn't running at all.  Can't seem to figure out why ...10:44
ZipCPUI tied SIM to 0 ... didn't seem to help.10:44
ZipCPUIt's as though ... the or1k_board_uart_base for mor1kx-generic is pointed at the wrong address ..10:47
ZipCPUor1k-elf-readelf shows _or1k_board_uart_base to be at 0x0f5a410:54
ZipCPUwhereas the interconnect places it at  .... is it 0x90000000?10:55
kc5tjaSMDhome1: I've been using git since before github existed; I *STILL* get rebasing and merge resolution wrong.  It's not just you.11:08
kc5tjaZipCPU: Thanks: because you mentioned "SIM to 0", I now have The Fixx's "Saved by Zero" song stuck in my head.11:13
kc5tja(Not that I'm complaining; one of my fonder memories from the mid- to late-80s. ;) )11:13
ZipCPUkc5tja: Did you see this one?
kc5tjaOMFG yes, that was a BRILLIANT episode!11:29
ZipCPUOr how about my recent theme song:
kc5tjaThe video is unavailable.  :(12:26
ZipCPUOops ... the last characcter is supposed to be a capital I (eye), not a lower case ell.12:28
ZipCPUAnd OpenRISC is most definitely *not* getting 1 DMIPS/MHz ...14:06
ZipCPUkc5tja: Do you know enough about RISC-V to support a same (or similar) test?14:06
kc5tjawhile I got the GCC compiler working for RV64G, I have no way of running the code.14:22
ZipCPUI'll take that as a, "No."  Realistically, I'd need the 32-bit compiler running, and a working simulator that the community felt was "representative"--whatever that means.14:23
olofkZipCPU: I think you can run dhrystone on picorv32 quite easily17:36
olofkpicorv32 might not be the fastest risc-v implementation, but it's at least something17:36
olofkI'm booked at hotel Re Enzo now btw. Anyone else staying there?17:37
kc5tjapicorv32 has an average of 4 CPI, so you figure you can estimate Rocket performance by dividing time measurements by four (as appropriate for the benchmark in question)17:56
ZipCPUolofk: Hotel Re Enzo ... in Italy?20:29
ZipCPUOh, and did you get the news that I have dhrystone measures for mor1kx-generic?  or that the UART now works on mor1kx-generic?  (at least, it works here ...)20:31
-!- mboehnert1 is now known as mboehnert23:26
--- Log closed Sun Aug 28 00:00:45 2016

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