| --- Log opened Sat Aug 27 00:00:32 2016 | ||
| --- Day changed Sat Aug 27 2016 | ||
| -!- kc5tja_ is now known as kc5tja | 04:34 | |
| mor1kx | [mor1kx] spacemonkeydelivers opened pull request #38: Introducing Performance Counter Unit (master...master) https://github.com/openrisc/mor1kx/pull/38 | 07:33 |
|---|---|---|
| SMDhome1 | Seems like I messed up w/ merging master to my fork and that's why I got lots of old commits in this pull request | 07:38 |
| SMDhome1 | Let's just agree I don't know how to use git/github | 07:55 |
| * ZipCPU mutters something unintelligible about the 16550 interface | 08:07 | |
| ZipCPU | Anyone know where I can find and control the arguments given to Verilator? | 08:31 |
| ZipCPU | That is ... from within fusesoc? | 08:32 |
| SMDhome1 | try build/mor1kx-generic/sim-verilator/verilator.make.log | 08:35 |
| ZipCPU | Strange ... I don't have that file. | 08:35 |
| SMDhome1 | but do you have build directory? | 08:36 |
| ZipCPU | Yes, and a sim-verilator directory within it even. | 08:39 |
| SMDhome1 | ZipCPU for it appears immidiately after running fusesoc --sim=verilator mor1kx-generic | 08:43 |
| ZipCPU | You mean in the text that I can't read 'cause it's yellow on a white background? ;) | 08:49 |
| ZipCPU | No ... it's not there. | 08:50 |
| ZipCPU | For some reason, the mor1kx-generic UART isn't running at all. Can't seem to figure out why ... | 10:44 |
| ZipCPU | I tied SIM to 0 ... didn't seem to help. | 10:44 |
| ZipCPU | It's as though ... the or1k_board_uart_base for mor1kx-generic is pointed at the wrong address .. | 10:47 |
| ZipCPU | or1k-elf-readelf shows _or1k_board_uart_base to be at 0x0f5a4 | 10:54 |
| ZipCPU | whereas the interconnect places it at .... is it 0x90000000? | 10:55 |
| kc5tja | SMDhome1: I've been using git since before github existed; I *STILL* get rebasing and merge resolution wrong. It's not just you. | 11:08 |
| kc5tja | ZipCPU: Thanks: because you mentioned "SIM to 0", I now have The Fixx's "Saved by Zero" song stuck in my head. | 11:13 |
| kc5tja | (Not that I'm complaining; one of my fonder memories from the mid- to late-80s. ;) ) | 11:13 |
| ZipCPU | kc5tja: Did you see this one? https://www.youtube.com/watch?v=g8vHhgh6oM0 | 11:27 |
| kc5tja | OMFG yes, that was a BRILLIANT episode! | 11:29 |
| ZipCPU | Or how about my recent theme song: https://www.youtube.com/watch?v=LI_Oe-jtgdl | 11:43 |
| kc5tja | The video is unavailable. :( | 12:26 |
| ZipCPU | Oops ... the last characcter is supposed to be a capital I (eye), not a lower case ell. | 12:28 |
| ZipCPU | DHRYSTONE WORKS!!! (UART TOO!) | 13:38 |
| kc5tja | Yay!! | 13:49 |
| ZipCPU | And OpenRISC is most definitely *not* getting 1 DMIPS/MHz ... | 14:06 |
| ZipCPU | kc5tja: Do you know enough about RISC-V to support a same (or similar) test? | 14:06 |
| kc5tja | while I got the GCC compiler working for RV64G, I have no way of running the code. | 14:22 |
| ZipCPU | I'll take that as a, "No." Realistically, I'd need the 32-bit compiler running, and a working simulator that the community felt was "representative"--whatever that means. | 14:23 |
| olofk | ZipCPU: I think you can run dhrystone on picorv32 quite easily | 17:36 |
| olofk | picorv32 might not be the fastest risc-v implementation, but it's at least something | 17:36 |
| olofk | I'm booked at hotel Re Enzo now btw. Anyone else staying there? | 17:37 |
| kc5tja | picorv32 has an average of 4 CPI, so you figure you can estimate Rocket performance by dividing time measurements by four (as appropriate for the benchmark in question) | 17:56 |
| ZipCPU | olofk: Hotel Re Enzo ... in Italy? | 20:29 |
| ZipCPU | Oh, and did you get the news that I have dhrystone measures for mor1kx-generic? or that the UART now works on mor1kx-generic? (at least, it works here ...) | 20:31 |
| -!- mboehnert1 is now known as mboehnert | 23:26 | |
| --- Log closed Sun Aug 28 00:00:45 2016 | ||
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