IRC logs for #openrisc Saturday, 2016-08-13

--- Log opened Sat Aug 13 00:00:23 2016
kc5tjaWell, that sucks.  The S64X7 is too big to fit even on an iCE40-HX8K device.01:45
kc5tjaJust *barely* won't fit.01:45
kc5tjaI can probably widdle it down to fit on an 8K device by replacing the ALU with the hand-crafted ALU I wrote a while ago.01:46
kc5tjaAnd I still need to implement a 64-bit to 16-bit Wishbone bridge.01:46
kc5tjaI'll do that tomorrow.  At least what I have should work on the Xilinx chip I have.01:47
kc5tjaManaged to get S64X7 design to fit on HX8K device; Xilinx says a lot of latches exist, so the design can still be shrunk.15:07
ZipCPUkc5tja: Can you point me at any good MISC papers?16:49
kc5tjaNot really; MISC was never taken seriously by industry or academia.  Everything I know about MISC came from study of the (scattered) material on website.17:33
kc5tjaAlthough, there is this book, where I saw the term first used.
kc5tjaIt was in reference to the MISC M17 CPU.17:34
kc5tjaAlthough, my architecture is more closely related to the F21 than it is the M17.17:43
ZipCPUAll of the MISC material I've found from Google searching, to include the M17, appears to be based around a stack machine.18:04
ZipCPUIs this your understanding of what a MISC machine is?18:05
ZipCPUOr ... perhaps accumulator based, but not register based.18:05
kc5tjaVery nearly all MISC computers are stack architectures, and of those, almost all of those are built for Forth.18:33
kc5tjaS64X7 is a Forth CPU, whereas my S16X4 is not.  But both are MISC architectures.18:34
kc5tjaI suppose some accumulator-based machines could fit the bill as well; PDP-8 comes to mind.  I'd definitely say Data General Nova does too.18:35
kc5tjaBut, Nova is right on the edge of not being MISC.18:35
--- Log closed Sun Aug 14 00:00:24 2016

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