--- Log opened Wed Jul 27 00:00:57 2016 | ||
stekern | ZipCPU: I'd put the caches in the "bump" in your approach | 02:31 |
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stekern | ... and I'd have a "bump" on both the ibus and the dbus (if that's what the "two implementations" meant) | 02:32 |
ssvb | olofk, poke53281: I have updated the https://pixman.miraheze.org/wiki/OpenRISC_Support#Known_problems section to also list jor1k | 10:53 |
ssvb | regarding the toolchain in general, is there a good reason why or1k-elf and or1k-linux-musl use different branches in the https://github.com/openrisc/or1k-gcc repository? | 10:54 |
ssvb | the malloc problem is only reproducible in qemu but not in jor1k, so it probably makes sense to debug qemu and try to fix it | 10:56 |
Finde | https://www.reddit.com/r/Android/comments/4uuiuf/why_is_the_proprietary_arm64_preferred_to_the/ | 11:34 |
Finde | lol | 11:34 |
kc5tja | Morning. Just waiting for my morning meeting before heading into work. | 12:07 |
ZipCPU | This was a surprise: I got a certificate expired notice for https://www.opencores.org:443, yet later had complete success with https://opencores.org:443. | 16:21 |
ZipCPU | Supposedly, th certificate for the first was for "*.opencores.org", yet it expired Aug 25, 2013. | 16:21 |
olofk | ssvb: Thanks for the update. Don't have a clue about the different branches | 16:59 |
ssvb | olofk: ok, I'll just try to test if the musl branch also works for or1k-elf | 17:10 |
ssvb | from the practical point of view, I'm most interested in the 'microcontroller' variant of OpenRISC because it is used in Allwinner SoCs | 17:11 |
olofk | stekern: You know the history of these branches? | 17:12 |
olofk | The musl tags seem to be a bit older | 17:14 |
--- Log closed Thu Jul 28 00:00:59 2016 |
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