IRC logs for #openrisc Monday, 2016-07-25

--- Log opened Mon Jul 25 00:00:54 2016
-!- John is now known as Guest7682312:46
mafm(only 2 parts so far, not complete)12:48
mafmdid anybody try to put RISC-V chips on FPGAs which don't need 41GB of Vivado installation, license keys, etc?12:50
mafmI think that there are none or not many which work only with FOSS tools, but perhaps something more user friendly and less crazy...?12:51
kc5tjamafm: I'm attempting to build my own RISC-V implementation suitable for use on an iCE40-HX4K part.13:49
kc5tjaI'm using Project IceStorm toolchain to implement it.13:49
mafmkc5tja: so you don't know if it works, yet?13:53
mafmdo you think that it can be used by somebody with little idea?13:53
mafmI am not sure why in sifive recommend some boards and not others for different systems, for example13:54
kc5tjamafm: I'm still writing the Verilog.  It definitely doesn't work yet.14:17
kc5tjamafm: It will be released on Github when done, and packaged via FuseSoC as well.  You would need to know how to work with Verilog in order to synthesize it, and code for 64-bit RISC-V to program for it.14:18
kc5tjaBut it should be more or less self-contained (kind of like picorv32 is) when finished.14:19
kc5tjaSpeaking of which, picorv32 is an earlier 32-bit version of RISC-V, but it isn't conformant with contemporary privilege specifications (its interrupt handling is quite different from the current specs).14:20
mafmkc5tja: ok, thanks.  sounds quite a bit over my head at the moment :D15:01
kc5tjamafm: My goal is to have a kit that folks can purchase, and just solder everything together and apply power.15:03
kc5tjaBut that's longer term.15:03
kc5tjaI need a working proof of concept first.  ;)15:03
mafmI see15:05
olofkpicorv32 is of course already packaged for FuseSoC as well :)18:06
olofkIt doesn't run Linux though18:06
olofkSo let's hope that kc5tja implements the 64-bit Linux-capable RISC-V core on this chip without losing his sanity :)18:07
olofkI probably need to sleep now to avoid losing my sanity.18:08
olofkOr I need to find whoever programmed children to wake up 5:30 in the morning and send in a pull request to fix this strange bug18:09
kc5tjaolofk: The first iteration of the chip will only have M-mode, so won't be able to run LInux either.18:10
kc5tjaI would need to add Sv39 or Sv48 support before being able to support Linux, but that'll take a year unto itself, I think.  Paging MMUs are not simple beasts.18:10
kc5tjaI like to explain it as, "a glorified, 64-bit 6502."18:11
kc5tjaAlthough with the 4 CPI average performance, it's closer to describe it as a 64-bit Z-80.18:15
ZipCPUIs anyone interested in the Arty?  I just started an "openarty" project on open cores, and I'm testing a flash controller that runs at 100MHz (200 MHz system clock) on the Arty.  Yes, all of the above is wishbone compatible.20:22
kc5tjaCurrent status:
kc5tjaReally quite bummed actually.21:02
kc5tjaHalfway tempted to drop RISC-V and just go back to using MISC technology.21:05
ZipCPUReading your log, it sounds like you are really bummed.21:49
ZipCPUkc5tja:Remember the basic questions:21:53
ZipCPU1. What is old.21:53
ZipCPU2. What does the old lack.21:53
ZipCPU3. What is new.21:53
ZipCPU4 What does the new have that the old lacks.21:53
ZipCPU5. What performance improvement can be expected with the new.21:54
ZipCPUYou might find this sort of focus valuable.  Perhaps you wish to swap "old" with SiFive.21:55
ZipCPURe-evaluating your purpose is not a bad thing, though--and should probably be done periodically anyway.21:55
--- Log closed Tue Jul 26 00:00:56 2016

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