| --- Log opened Fri Jul 15 00:00:20 2016 | ||
| --- Day changed Fri Jul 15 2016 | ||
| ZipCPU|Laptop | stekern: Thank you for the examples. That's exactly the sort of logic I am trying to build. | 06:11 |
|---|---|---|
| stekern | ZipCPU|Laptop: I've spent a couple of hours weeding out bugs in both of those files ;) | 06:12 |
| ZipCPU|Laptop | Just hours? | 06:12 |
| stekern | heh | 06:12 |
| ZipCPU|Laptop | Yup. You understand me completely. ;) | 06:12 |
| olofk | wallento, ZipCPU|Laptop : Awesome! I've been meaning to do a UART thingie like that for a long time too | 10:33 |
| wallento | there is rdiez' stuff too | 10:33 |
| wallento | https://github.com/rdiez/uart_dpi | 10:33 |
| wallento | but I really wanted the UART experience on both sides ;) | 10:34 |
| olofk | kc5tja: Have you looked into etherbone, or any of the other CERN Wishbone projects? I think they have some infrastructure for external wishbone buses. Some of it is even in the upstream Linux kernel since Alessandro Rubini is quite involved with those things | 10:34 |
| olofk | wallento: Yeah. I haven't really looked at his stuff. Didn't feel like getting more involved with that guy | 10:35 |
| olofk | gtg. There's a city to explore outside! | 10:35 |
| wallento | enjoy boston | 10:36 |
| olofk | Thanks | 10:36 |
| olofk | Anyone need a souvernir? | 10:36 |
| kc5tja | olofk: No, never heard of it. | 10:38 |
| kc5tja | olofk: However, my externalized Wishbone doesn't really require software support. It's designed to be just a dumb export of the bus. | 10:38 |
| olofk | I think they have something like that too | 10:39 |
| kc5tja | olofk: Oh dear; wishbone-over-Ethernet? No thanks. That just wreaks of complexity. | 10:39 |
| kc5tja | It's just occurred to me that I have a total of three months to build a working Kestrel-3 prototype with ... *something*. | 10:55 |
| kc5tja | With the success rate I've been having building hardware, procuring hardware, or even just getting IDE tools to @#(%*ing run at all, this will not happen. >:( | 10:55 |
| kc5tja | icoBoard wants almost $150 for an FPGA board which still isn't equipped enough for my needs (and I'd need at least two), I can't get WebPACK ISE to license on my workstation, ... | 10:56 |
| kc5tja | I might as well toss in the towel for this up-coming RISC-V workshop. | 10:57 |
| ZipCPU | kc5tja: Actually, I've been running wishbone over ethernet for some time. It started as a wishbone over serial port project, but I then forwarded the serial port over the ethernet. | 12:19 |
| ZipCPU | Since then, I've made wishbone run over both the JTAG user interface as well as Digilent's 8-wire paralell DEPP interface. | 12:19 |
| ZipCPU | It's the first thing I get running on any new project. | 12:19 |
| kc5tja | I guess what I mean is, complexity == lots of LUTs, and I will not have that many to spare. | 13:33 |
| kc5tja | One of my long term goals is to make a Kestrel-3 with expansion slots using RapidIO. | 13:34 |
| kc5tja | Which is along the same lines as wishbone-over-X. | 13:34 |
| kc5tja | For the love of life, I just cannot find any specs on Etherbone or how it works under the hood. :( | 13:37 |
| kc5tja | Ahh, found a PDF at last. | 13:48 |
| kc5tja | Yeah, that's several hundred KB of VHDL, and that's not an insignificant amount of logic. Their definition of "simple" is quite different from mine. ;-) | 13:54 |
| ZipCPU | kc5tja: Let's see, my wishbone over serial port consumes about 812 6-LUTs--but that includes compression, which I would probably drop if I really wanted to get the LUT count down. | 14:37 |
| kc5tja | Right now, my ALU alone consumes 1800 LUTs, on a 3540 LUT device. I still haven't sized the instruction decoder yet. | 15:13 |
| kc5tja | I estimate around 300 minterms for the decoder so far. CSR registers are not yet specified either. | 15:13 |
| kc5tja | I'm sure hoping I can fit everything. :) | 15:14 |
| ZipCPU | kc5tja: This is still the Kestrel-3, the 64-bit RISC-V CPU you are working on, right? | 15:58 |
| kc5tja | Kestrel-3 is the computer in which the CPU will be used, yes. The CPU's name is Polaris. | 15:58 |
| kc5tja | If it turns out I need to shrink the ALU, I think the first thing to go is fast bit-shifts. But, I sure don't want to discard those, because Kestrel-3 is a graphics-heavy machine. | 15:59 |
| kc5tja | (no text mode) | 15:59 |
| ZipCPU | kc5tja: If I remember correctly from your web pages, you have multiple "slaves" on a physical bus acting in concert, no? If not, how on earth are you able to handle a "graphics heavy" machine if your CPU is filling up the FPGA? | 16:01 |
| kc5tja | One FPGA is the CPU. One is the I/O chip (including video display core). One is the RAM controller. All three FPGAs are tied together over a common bus (an externalized, 16-bit Wishbone bus). | 16:02 |
| ZipCPU | That external bus ... you're running it at 50MHz, no? | 16:03 |
| kc5tja | The CPU and I/O controller compete for the bus using a round-robin bus arbitration mechanism. | 16:03 |
| kc5tja | That was the original plan, but I may have to drop to 25MHz. | 16:03 |
| ZipCPU | And are you using the B4 spec? Are you using the pipelining mode within it? | 16:03 |
| kc5tja | As long as I can run it at 25MHz, everything should have enough i/O throughput to keep up. | 16:04 |
| kc5tja | It's based on B4, but it's not 100% compatible (B4 doesn't specify how to export the bus externally). | 16:04 |
| kc5tja | No, no pipeline support. | 16:04 |
| kc5tja | Each bus transaction takes two clock cycles (cycle 1 will drive the address bus, cycle 2 will be when we sample ACK). | 16:05 |
| ZipCPU | You must at least be pipelining the 64-bit accesses across the bus ... | 16:05 |
| kc5tja | So, total throughput is 12.5 mega-transfers per second, enough to keep up with most RAM technologies. | 16:05 |
| kc5tja | Nope. | 16:05 |
| ZipCPU | So that's 12.5MT/s at 16-bits/transfer? | 16:05 |
| kc5tja | Yes. | 16:05 |
| ZipCPU | Is there any reason you chose not to use the pipeline mode, to get closer to 25MT/s? | 16:06 |
| kc5tja | With 4 clocks per instruction, the CPU maxes out at 6.25 MIPS anyway, so no need to go faster. | 16:06 |
| kc5tja | Keeping the design deliberately very, very simple. | 16:06 |
| kc5tja | That means using relatively slow, easily accessible RAMs. | 16:06 |
| ZipCPU | 64k address space? | 16:07 |
| kc5tja | I'm looking at using a 70ns RAM, which means it can keep up at most with a 14MHz bus. So, restricting data flow to 12.5MT/s stays within the bounds. | 16:07 |
| kc5tja | 4.2GB address space (though laid out in an unconventional manner. 256 segments of 16MB each, spread out evenly in a 64-bit address space.) | 16:07 |
| kc5tja | Address bus contains A63-A54, A31-A1. | 16:07 |
| kc5tja | A53-A32 are ignored. | 16:08 |
| ZipCPU | Yet only 16 data lines? Are the address and data lines shared at all? | 16:08 |
| kc5tja | No. | 16:08 |
| kc5tja | Though, I've considered it. | 16:08 |
| kc5tja | But I decided against it because it would have added an extra cycle of latency per transfer. | 16:08 |
| ZipCPU | Forgive me if I ask so many questions, I find both your project and goals quite fascinating--although not my own. | 16:09 |
| kc5tja | No worries. | 16:09 |
| kc5tja | I enjoy talking about it. Frees my mind from work-day duldrums. :) | 16:09 |
| ZipCPU | My own project has been to design a "simple" computer for an FPGA. The goal has been to reduce the LUT count as much as possible. | 16:09 |
| ZipCPU | Then I started realizing you can purchase speed with LUTs ... so the tradeoff isn't quite as simple as I had first imagined it to be. | 16:10 |
| kc5tja | Yeah. My original goal for the project was to target the 1,000,000-gate FPGA in my Nexys-2 board. | 16:10 |
| kc5tja | There, I would have integrated everything into a single Verilog design, and clicked a button, and gotten an instant computer. | 16:10 |
| ZipCPU | and now you've switched to an iCE40? | 16:10 |
| kc5tja | That's how I made my Kestrel-2 (16-bit, stack-architecture predecessor to the Kestrel-3). | 16:10 |
| kc5tja | Yes, because I cannot get the Webpack ISE tools to license on my Ubuntu laptop. :( | 16:11 |
| ZipCPU | Really? I managed to get it done on my Ubuntu desktop somehow ... | 16:11 |
| kc5tja | So I decided to go the open-source route, but since no existing FPGA boards exist which meet my needs, I had to go and build my own. And _that_ meant making a backplane bus to tie everything together. | 16:11 |
| kc5tja | The binary runs, but doesn't do anything. | 16:11 |
| kc5tja | It exits with result code 0. | 16:11 |
| ZipCPU | Did you get the license? | 16:12 |
| kc5tja | No. | 16:12 |
| kc5tja | It just dies. | 16:12 |
| kc5tja | It's like someone wrote a several megabyte main() {} program. | 16:12 |
| ZipCPU | Okay, there was a problem pulling firefox up to get the license. When you click on get license, it tries to load firefox and there's an incompatibility. | 16:12 |
| ZipCPU | I googled it once, and so got past it ... | 16:12 |
| ZipCPU | Just don't ask me how any more. I've still got Google if I need to do it again. ;) | 16:13 |
| kc5tja | Ahh, if you have any information (can remember any links), that would be very helpful. | 16:13 |
| kc5tja | Especially since I only have 3 months to somehow get something I can demo at RISC-V workship #5. | 16:13 |
| kc5tja | I remember googling about it, but got a lot of unhelpful references to Xilinx forum queries. | 16:13 |
| kc5tja | I will try again though. | 16:13 |
| kc5tja | That said, I do still want to eventually target the iCE40s though. I'm all about supporting open-source hardware, especially since they don't make the NExys-2 boards anymore. | 16:14 |
| ZipCPU | Yes, they seem to be on the Nexys-4 DDR these days ... | 16:18 |
| kc5tja | Yeah. And I'd be fine-ish with that were it not for the fact that I have a *perfectly* working Nexys-2 board on my desk. ;D | 16:36 |
| kc5tja | Anyone knows of a single-file equivalent to grin that does not require pip to install? | 17:16 |
| kc5tja | This would make searching through logs a bit easier on the API staging node, but I don't want to install pip just to install grin. | 17:18 |
| kc5tja | errrg!!! Wrong channel again. | 17:38 |
| kc5tja | Sorry. | 17:38 |
| kc5tja | Though, I did manage to solve my problem. :) | 17:38 |
| ZipCPU | Here's a decent single file equivalent to grin: http://i.ebayimg.com/00/s/NTAwWDUwMA==/z/uFoAAOSwpDdVQ-Vc/$_1.JPG | 17:57 |
| --- Log closed Sat Jul 16 00:00:41 2016 | ||
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