IRC logs for #openrisc Monday, 2016-06-13

--- Log opened Mon Jun 13 00:00:51 2016
mor1kx[mor1kx] olofk opened pull request #35: Remove empty parameter lists (master...master)
olof_imphil: Good thinking with the conditional filesets07:33
mor1kx[mor1kx] skristiansson pushed 1 new commit to master:
mor1kxmor1kx/master 5b10fe0 Olof Kindgren: Remove empty parameter lists07:34
stekernnice that github has added the possibility to do squash-and-commit pulls07:34
repmovsdI am looking for a disassembler for OpenRisc.07:36
stekernso you can merge single patches without getting a merge commit07:36
repmovsdIs there a way to make objdump work with it?07:36
stekernand merge pull requests that has "fix-up" commits in them07:36
imphilolof_, even better would be xilinx not having two major revisions in half a year of their MIG, but I guess that's wishful thinking07:38
stekernrepmovsd: if you install a openrisc toolchain you'll get an objdump with that07:38
imphilolof_, seems to be impossible after years of development to have a relatively stable API for a memory interface.07:39
olof_imphil: I can't believe that they're still doing that. I had the same problems four years ago, and was almost ready to forgive them now, because I thought they had learned07:39
repmovsdstekern: Thanks. Is there a working windows port?07:40
olof_imphil: No, it's completely crazy. And in my experience they are sometimes subtly changing the behaviour of a signal or even reversing the meaning between two FPGA families07:40
stekernrepmovsd: don't think so, easiest is probably to use a linux vm if you're a windows user07:41
imphilolof_, once they changed the polarity of the reset signal from active high to active low. fun debugging that.07:41
olof_imphil: We should start a support group for MIG users07:41
repmovsdstekern: I see. I try to install the toolchain and see how it goes :)07:41
stekernimphil: really? they must really hate their users...07:41
imphilolof_, looks like there were "stable" years, but now they're picking up speed again. 2016.2 comes with v4.007:41
olof_There have been some improvements in the open source controllers, but the problem is that the Vendor-generated ones is starting to contain a lot of undocumented primitives and stuff that you're not really supposed to know about07:42
olof_I think a good compromise would be if they started supporting the DFI standard, so we could implement a proper controller, and they can keep their crazy proprietary nonsense on the phy side07:43
olof_I know that Altera has been moving in this direction, but as usual, if one of the big FPGA vendors support a standard, the other one refuses to do the same07:44
olof_Why doesn't my mor1kx start executing from OPTION_RESET_PC? Looks like it just tries to read from 007:57
stekernhmm, haven't seen that08:02
olof_I've used signal tap now and see that it the fetch module enters the read state, but just asks for address 008:04
wallentois the reset correct?08:04
olof_I'm a bit worried this is because I don't have a proper reset signal08:04
olof_I'm just creating one with a shift reg08:04
wallentothat should be okay usually, right?08:04
wallentobecause its synchronous IIRC08:05
wallentootherwise you need to create a pulse out of your reset08:05
wallentodetect the falling edge of the reset and generate a pulse08:05
wallentoI think oh! contains the building blocks for such things08:06
olof_I already have those things. I'm using a synchronous release asyncronous set module08:07
olof_But I don't have an external reset input08:07
olof_ok, one step further. At least the PC is set to 0xf0000000 now08:34
olof_Fuck yeah! It was a reset problem all along. mor1kx or some other core requires a reset to work08:45
olof_And for some reason, my first attempt didn't work08:45
ZipCPUIs anybody building ORPSOC on an S6 these days?  I'm looking for a LUT count ...13:47
olofkZipCPU: We have builds for the Atlys board, and I have a WIP for the lx9 microboard15:51
ZipCPUolofk: Here's what I'm trying to do ... as part of putting an abstract together, in the hopes of presenting at ORCONF, I really need something to compare with.15:52
ZipCPUI can make various ZipCPU builds, but I'd like to compare their LUT counts with ... other options.15:52
ZipCPUBrakefields work gives me some wonderful point data, but ... it's just a spreadsheet.  It's hard to compare apples to apples.15:53
ZipCPUI'd like to compare LUT counts between the ZipCPU and ... other CPU's.  But ... LUT counts with divide instructions?  Multiply instructions?  Pipelines?  MMUs?  Instruction caches, of what size?15:53
ZipCPUThe options seem endless.15:53
ZipCPUStill ... where would I find a build for an Atlys or lx9 board.  I might find either (or both) instructive.15:54
olofkOh yes. The double-edged sword of configurability15:54
olofkWe have been talking about creating a OpenRISC base system. Something perhaps with a sane configuration of mor1kx, 32MB RAM, gpio, UART, SPI and i2c15:55
ZipCPUSigh ... that's another difficulty.  How do you compare in the presence of (different) peripherals?15:56
olofkThat would give us something of a yard stick at least15:56
olofkMost modern synthesis tools are at least capable of giving you LUT count for each sub module.15:57
ZipCPUIt's a start, although ... every FPGA board I've worked on has had Flash and block RAM, not as many have had proper DDR RAM.15:57
ZipCPUTrue, although I've learned not to trust XST with ISE.  It leaves too much logic at the top.15:57
olofkFor many years, Xilinx themselves told people to use Synplify instead, so you're not alone in not trusting xst :)15:58
ZipCPUDoes mor1kx offer internal peripherals as well?  My initial version of the ZipCPU had a ZipSystem associated with it that offered 3x timers, an interrupt controller, 8x counters, and some watchdog timers.15:59
ZipCPUI had to trim down later when that was too much for some applications.15:59
olofkYou can remove some things, but the or1k spec defines at least the interrupt controller and timer iirc15:59
ZipCPUMakes sense ... it is kind of hard to get a interval timer driven multi-processing system running without those two.16:01
olofkstekern can probably correct me here, but I think that removing caches, MMUs, FPU and divider will get you close yo minimum size16:01
ZipCPUIf you remove all caches, are you still pipelined?16:01
olofkNot sure actually16:02
ZipCPUIn my case, removing all caches removes the pipeline contention logic as well.16:03
olofkYou can configure the wishbone buses with our without bursts, so in theory, I guess you could have a 8 word cache just to make a burst access to the memory16:03
olofkBut I would have to check the implementation (or preferably ask someone who knows) to be sure16:04
olofkTrying to think of all things that are great with FuseSoC so I can put it on my poster for the RISC-V conference16:05
LaksenHow do you do the interconnect stuff or doesn't it do that anymore?16:09
olofkLaksen: It doesn't do any automatic interconnects. I think it's too complex to handle inside of FuseSoC. My idea is instead to use external tools that can do this, for example with IP-XACT descriptions16:11
olofkKactus2 is getting there, but I would like to have a command-line flow as well, so it can be done as a step during the build process16:12
olofkFuseSoC (or rather some of the cores that is FuseSoC-compatible) does however have some utilities to make it easier to create interconnects for Wishbone-based systems16:13
olofkIt currently generates verilog code for the interconnect, and the next step is to also generate an IP-XACT description so that it can be dropped directly into a IP-XACT enabled tool16:13
ZipCPUolofk: In my minimum configuration, I can get the CPU down to 1215 LUTs, and a minimal SoC that fits in a Spartan LX4 in 2,220 LUTs.16:18
olofkZipCPU: OpenRISC isn't all that small, but it would be interesting to compare it to picorv3216:21
olofkHave you tried building zipcpu for the iCE40 devices?16:21
olofksorry. Slipped on the keyboard16:22
ZipCPUolofk: No, I've never tried building the ZipCPU for anything but Xilinx.  It should build, though, I haven't used any Xilinx specific primitives.  That said, switching vendors is always an adventure.16:27
olofkZipCPU: Yes, it is. But FuseSoC makes it easier to port designs to new targets16:29
olofkAt least it says so on the poster :)16:29
ZipCPU(Looking up picorv32 now ...)16:38
ZipCPUGosh ... 750 LUTs?16:41
ZipCPUOkay, it says 750-2000 ... and that's a broad range, but still ...16:43
olofkYou can build picorv32 with FuseSoC if you want to try it out :)16:51
ZipCPUThanks!  I'm still digging through the RISC-V spec to find out what's different, though.16:52
olofkI think they put a lot of thought and effort into streamlining the ISA. Many of the ideas there is the same that we had for a upcoming or2k ISA16:56
ZipCPUWell, the spec certainly reads like they put a lot of thought into it--especially since it records why they made their various choices.16:56
LaksenAnyone have experience using IP-XACT stuff from Vivado in Kactus2?16:57
olofkYes. I heard it's a great read in that regard. Haven't dug too deep myself16:57
LaksenI can't get it to find my components :(16:57
olofkLaksen: Yes, I know that the guys from Antmicro are using a combination of Vivado and Kactus for the Axiom camera project16:57
olofkI have managed to get Kactus2 to read some Xilinx IP, but unfortunately the compatibility isn't very good. Both tools define their own tags that the other don't understand16:58
olofkAnd starting with Kactus 3, they have switched to using only IP-XACT 2014, which Vivado doesn't handle16:59
olofkSo it's a bit of a mess16:59
LaksenSounds like it :(16:59
olofkBut Kactus 2.8 can at least read some Vivado ip16:59
LaksenYeah, I remember it sort of being able to use Logicore ip17:00
olofkYeah. I like IP-XACT because it's the best hope we have for a vendor-independent standard, but the standard itself is horrible in many places17:00
olofkBut FuseSoC can read IP-XACT 1.4, 1.5, 2009 and 2014 :)17:01
LaksenYeah it's a great idea, but pretty extreme17:01
LaksenHehe how much of the standard does it support?17:01
olofkFuseSoC knows enough to read filesets from IP-XACT files, which is the only thing that it currently uses from IP-XACT17:02
olofkThat works quite well17:02
olofkThe internal library that FuseSoC uses to read IP-XACT ( handles also most of the register parts and some of the bus interfaces, but FuseSoC can't use that yet17:03
olofkTime to sleep now17:04
LaksenI might have to stress test it :)17:06
LaksenWorking on this thing right now:
olofkvscale is supported in FuseSoC, btw17:08
olofkI think there are cores for five different risc-v implementations in the standard core library17:08
LaksenHehe guessed it was. I just became inspired to try out some Vivado packaging :)17:08
olofkIf you have an IP-XACT file for vscale, I'm happy to take a look at it to showcase the FuseSoC IP-XACT integration17:09
olofkThere aren't many good examples right now17:09
LaksenI can for sure send it, but I haven't tested it yet. That's why I'm sad only Xilinx has this nice a flow17:09
LaksenGot no series 7 boards at home :(17:09
olofkFuseSoC makes it easy to test your designs with multiple simulators17:10
* olofk is turning off marketing mode17:11
--- Log closed Tue Jun 14 00:00:52 2016

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