| --- Log opened Sun May 22 00:00:17 2016 | ||
| shorne | ok, I had some time to compare gcc and gdb. I figured out how to read the stuff calling convention in gcc. What I figured out by reverse engineering the assembly is pretty close to gcc. | 03:52 |
|---|---|---|
| shorne | The one was was worried about is why vecrod are handled strange, but it seems to be how vector mode defined in gcc. gcc/stor-layout.c in vector_type_mode() | 03:54 |
| shorne | It seems openrisc actually falls back to some gcc default behavior for returning structures and vectors. | 03:55 |
| shorne | definned gcc/targhooks.c : default_return_in_memory | 03:56 |
| shorne | I posted the latest changes to my git pull request. https://github.com/openrisc/binutils-gdb/pull/2/commits/044bcb88fc7e6feca6a49da4b7f1cd0d701810a7 | 04:14 |
| shorne | will look into other failures | 04:14 |
| SMDhome | Trying fusesoc with verilator and getting errors like: verilator/tb.cpp:89:29: error: ‘class Vorpsoc_top’ has no member named ‘v’ | 08:29 |
| SMDhome | Has anyone seen that before? | 08:49 |
| shorne | SMDhome: no, but I replied to your PM from SMDnote, let me know if you see it, you can ask any followup questions on gdb in the room if you want | 08:52 |
| SMDhome | Seems like dhrystone hangs on current mor1kx Oo | 11:18 |
| SMDhome | Seems there is a bug in mor1kx .____. | 12:54 |
| olofk_ | SMDhome: Are you running mor1kx-generic under verilator? | 13:31 |
| olofk_ | When you get the " error: ‘class Vorpsoc_top’ has no | 13:31 |
| olofk_ | member named ‘v’" errors | 13:31 |
| SMDhome | olofk_: nope, I tried verilator and got that error with no "v" in class | 13:31 |
| -!- olofk_ is now known as olofk | 13:31 | |
| olofk | SMDhome: But which system did you run? | 13:31 |
| SMDhome | I guess I run iverilog sim instead. Mor1kx-general | 13:32 |
| SMDhome | https://github.com/openrisc/mor1kx/issues/33 | 13:32 |
| olofk | You mean mor1kx-generic ? | 13:32 |
| SMDhome | yep. sorry | 13:32 |
| SMDhome | I don't know for sure, but flag in "x" state seems wrong | 13:32 |
| SMDhome | Also I'd like to run verilated version | 13:33 |
| olofk | SMDhome: How did you run it? "fusesoc sim --sim=verilator mor1kx-generic --elf-load /path/to/elffile" ? | 13:34 |
| SMDhome | http://pastebin.com/tkiaDY9j | 13:34 |
| SMDhome | verilator is built from latest sources | 13:35 |
| SMDhome | olofk: can I get .vcd with fusesoc? | 13:49 |
| olofk | SMDhome: It's usually with --vcd | 13:50 |
| SMDhome | thanks, I'll try to debug dhrystone thing but it would be nice if someone could try to reproduce it | 13:51 |
| olofk | But only if the system has implemented vcd dumping, which most systems in the standard library does | 13:51 |
| olofk | SMDhome: I'll give it a shot when I get the time | 13:51 |
| SMDhome | I think there is a problem with rf and pipeline itself, I'll update ticket with .vcd file | 14:23 |
| SMDhome | Updated ticket | 14:35 |
| SMDhome | mor1lx_lsu_cappuchino:327 line, i got {1, 10} at switchcase and then fail to default. Is that planned or not? | 14:48 |
| SMDhome | something's wrong while bypassing results imho, but I need someone to confirm that. I'll continue tomorrow | 15:08 |
| olofk | SMDhome: I can't reproduce the verilator problems you are seeing | 16:04 |
| olofk | I'm updating my verilator installation to latest git head just to make sure | 16:05 |
| olofk | SMDhome: If you see undefined signals in the VCD, you could try to set OPTION_RF_CLEAR_ON_INIT=1 on mor1kx. That sets the initial register values to 0 instead of being undefined | 16:09 |
| SMDhome | olofk: they're defined, but something's wrong with results bypassing | 16:11 |
| SMDhome | S 00006e24: 84a40000 l.lwz r5,0x0000(r4) r5 = 000178ec flag: 1 | 16:11 |
| SMDhome | S 00006e28: a842feff l.ori r2,r2,0xfeff r2 = fefefeff flag: 1 | 16:11 |
| SMDhome | S 00006e2c: e0c51000 l.add r6,r5,r2 r6 = xxxxxxxx flag: 1 | 16:11 |
| SMDhome | S 00006e30: aca5ffff l.xori r5,r5,0xffff r5 = b1b8ffxx flag: 1 | 16:11 |
| olofk | SMDhome: Yep. With latest verilator I get the same errors as you got | 16:12 |
| olofk | Need to find out what changed and see if I can make it compatible with old and new versions | 16:12 |
| olofk2 | Stupid internet connection | 17:09 |
| olofk2 | SMDhome: I fixed the verilator issues | 17:09 |
| olofk2 | Edit ~/.local/share/orpsoc-cores/systems/mor1kx-generic/bench/verilator/tb.cpp and replace all "top->v->" with "top->orpsoc_top->" | 17:11 |
| olofk2 | Not sure if this works for older versions though, so I don't want to check in the changes | 17:13 |
| olofk2 | Anyone with a slightly older verilator who could check this? | 17:15 |
| olofk2 | Slighly older probably means 3.882 or older | 17:17 |
| olofk2 | gtg | 17:19 |
| SMDhome | olofk: thanks, it works now, even with dhrystone bin, but afaik iverilog sim is more precise | 23:19 |
| --- Log closed Mon May 23 00:00:19 2016 | ||
Generated by irclog2html.py 2.15.2 by Marius Gedminas - find it at mg.pov.lt!