IRC logs for #openrisc Thursday, 2016-05-19

--- Log opened Thu May 19 00:00:13 2016
wallentostolar: normally you want to share them with similar instructions to make decoding in hardware more efficient01:30
wallentobut in you case you need to find a new one01:30
wallentofor such cases l.cust1 can be used for example01:31
SMDhomewallento: hi, who's responsible for the openrisc specification and I wonder if a new one should be expected?01:34
wallentoSMDhome: The community actually01:34
wallentoThere is a wiki page with candidates01:34
wallentoThe proposals are numbered and we have had some mails before01:35
wallentounfortunately I was not able to follow up all mails01:35
wallentodo you have some proposals?01:35
wallentoIf so, you should send them for discussion to the mailing list01:35
wallentoI hope we can fix version 1.2 this year01:36
SMDhomenot yet, I still don't have a full picture of what's going on in my mind, I guess I need some time)01:37
wallentofeel free to drop any idea to the list, there will most probably not be another revision for the next years :)01:42
SMDhomeDoes soc with 4 mor1kx with cappucino pipeline fit into average fpga?01:46
wallentoyes, it should01:57
wallentoI am still integrating with the nexys4 ddr board02:11
wallentowhen I find time, it will be SMP multicore02:11
SMDhomewallento: were there any ideas/attempts/etc to come up with reference soc/devboard?02:14
wallentothere was one02:14
wallentoessentially this is what I am planning:02:14
wallentoabstract the system from the actual board and build a generic "tile" with SMD mor1kx in there02:15
wallentothis tile includes a configurable core information module, that the software can query for the board settings and features02:15
wallentonexys and arty are my first references02:16
wallentoso its a reference design02:16
wallentoand not one board02:16
SMDhomeAnd is there any milestone or final goal to go to?02:22
wallentoThis is my goal for now02:42
wallentowe started the tutorials:
wallentoplan is to have them for multiple boards, with prebuilt bitstream02:42
wallentoso that the quick start experience gets significantly improved02:42
SMDwrkolofk: can I get verilog $display() things with fusesoc somehow?04:46
olofkSMDwrk: Yeah, that should work.05:24
SMDwrkbut as far as I see for every launch of fusesoc it downloads mor1kx-generic from the git and then runs it. Can I use local copy and modify it?05:24
olofkSMDwrk: I'll answer your question about how to use your custom mor1kx as well here05:24
olofkCopy ~/.local/share/orpsoc-cores/cores/mor1kx.core to the root of your local mor1kx clone05:25
olofkRemove the [provider] section, and voila, you have made your first fusesoc core :)05:26
olofkNow, there are a few ways to make this core override the one in the standard library05:26
olofkThe easiest way is to launch with 'fusesoc --cores-root=/path/to/your/mor1kx ...'05:27
olofkIf you don't want to write this everytime, you can create a fusesoc.conf in your working directory05:27
olofkYou can start by copying the one from ~/.config/fusesoc/fusesoc.conf05:28
olofkAnd then add the path to your local core(s) after the standard library in the cores_root parameter there05:28
olofkPaths are separated by space05:28
SMDwrkok, thanks05:29
SMDwrkAnd a result of $display() should be visible with other output of fusesoc, right?05:29
SMDwrkOk, great!05:31
SMDwrkAnd what do you think about printing total cycle count information after simulation ends?05:31
olofkSMDwrk: If you run with --trace_enable, you will get some instruction trace files in build/mor1kx-generic/sim-icarus. Would that be what you're looking for?05:32
SMDwrkyep, that's it, thanks!05:35
olofkSMDwrk: Excellent. So you're on track then?05:37
SMDwrkSeems so, thanks! Now  I estimate check perf impact of new branch predictor. Should I post results anywhere?05:38
olofkSMDwrk: Just put it on some paste service if you want us to look at them. If the predictor is added, I would guess that we want to put some kind of results in the mor1kx documentation05:42
SMDwrkI think it could be nice to have sort of blog/issue tracker to post openrisc related info there05:44
olofkWe used to put these things on the OpenCores wiki, but for now, perhaps just open an issue on the mor1kx github site05:45
SMDwrkOk, thanks. Speaking of my patch - it works wrong, need to fix it.05:50
wallentoolofk: verilator 3.884 released with the olof-feature!08:20
SMDwrkI'm bit confused: in mor1kx do we have decode -> decode-execute -> execute -> execute-ctrl -> ctrl thing?09:30
SMDwrkAnd decode-execute/execute-ctrl store information by clk edge?09:30
SMDwrkSo on simple recursive fibonacci c program with -O0 option I got: 5271 mispredicts with original predictor and 4192 with mine, total cond branches executed - 948211:01
SMDwrkBut compiling it with -O2 gives ~66% hitrate with old predictor and ~50% on new ._.11:40
wallentothats the weird thing about branch prediction :)13:51
SMDhomewallento: I think I need to take a look at asm generated and try to figure out why it happens13:54
SMDhomeand we definitely need a scheme of mor1kx, it's too complicated for a newbie to figure out what's going on there and which wire is which13:56
-!- Netsplit *.net <-> *.split quits: jeremybennett, olofk, nurelin14:26
-!- Netsplit over, joins: olofk, nurelin, jeremybennett14:27
olofkwallento: Ahh.. cool. Time to build a new verilator then :)15:16
olofkSMDhome: Yeah, a block diagram would be great. Not sure how much work it would be though15:16
SMDnoteI hope some tool would build it for me :315:17
olofkSMDnote: Yeah, let me know when you find that tool. I want it too :)15:28
SMDnoteI'm looking for it for about a year now, some people suggest ice/quartus and use its rtl scheme15:34
SMDnotemaybe not such a bad idea if it preserves all signal names15:35
olofkYeah, I'm often using the RTL schema to check that things are synthesized the way I intended, but it can of course be very messy for complex designs15:37
SMDnoteI'd like something rather simple with main blocks and interconnections between them15:44
SMDnoteand I want to see at what clock what changes15:45
--- Log closed Fri May 20 00:00:14 2016

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