| --- Log opened Thu May 19 00:00:13 2016 | ||
| wallento | stolar: normally you want to share them with similar instructions to make decoding in hardware more efficient | 01:30 |
|---|---|---|
| wallento | but in you case you need to find a new one | 01:30 |
| wallento | for such cases l.cust1 can be used for example | 01:31 |
| SMDhome | wallento: hi, who's responsible for the openrisc specification and I wonder if a new one should be expected? | 01:34 |
| wallento | SMDhome: The community actually | 01:34 |
| wallento | There is a wiki page with candidates | 01:34 |
| wallento | http://opencores.org/or1k/Architecture_Specification | 01:35 |
| wallento | The proposals are numbered and we have had some mails before | 01:35 |
| wallento | unfortunately I was not able to follow up all mails | 01:35 |
| wallento | do you have some proposals? | 01:35 |
| wallento | If so, you should send them for discussion to the mailing list | 01:35 |
| wallento | I hope we can fix version 1.2 this year | 01:36 |
| SMDhome | not yet, I still don't have a full picture of what's going on in my mind, I guess I need some time) | 01:37 |
| wallento | feel free to drop any idea to the list, there will most probably not be another revision for the next years :) | 01:42 |
| SMDhome | Does soc with 4 mor1kx with cappucino pipeline fit into average fpga? | 01:46 |
| wallento | yes, it should | 01:57 |
| wallento | I am still integrating with the nexys4 ddr board | 02:11 |
| wallento | when I find time, it will be SMP multicore | 02:11 |
| SMDhome | wallento: were there any ideas/attempts/etc to come up with reference soc/devboard? | 02:14 |
| wallento | there was one | 02:14 |
| wallento | essentially this is what I am planning: | 02:14 |
| wallento | abstract the system from the actual board and build a generic "tile" with SMD mor1kx in there | 02:15 |
| wallento | this tile includes a configurable core information module, that the software can query for the board settings and features | 02:15 |
| wallento | nexys and arty are my first references | 02:16 |
| wallento | so its a reference design | 02:16 |
| wallento | and not one board | 02:16 |
| SMDhome | And is there any milestone or final goal to go to? | 02:22 |
| wallento | This is my goal for now | 02:42 |
| wallento | we started the tutorials: https://github.com/openrisc/tutorials | 02:42 |
| wallento | plan is to have them for multiple boards, with prebuilt bitstream | 02:42 |
| wallento | so that the quick start experience gets significantly improved | 02:42 |
| SMDwrk | olofk: can I get verilog $display() things with fusesoc somehow? | 04:46 |
| olofk | SMDwrk: Yeah, that should work. | 05:24 |
| SMDwrk | but as far as I see for every launch of fusesoc it downloads mor1kx-generic from the git and then runs it. Can I use local copy and modify it? | 05:24 |
| olofk | SMDwrk: I'll answer your question about how to use your custom mor1kx as well here | 05:24 |
| SMDwrk | thanks | 05:25 |
| olofk | Copy ~/.local/share/orpsoc-cores/cores/mor1kx.core to the root of your local mor1kx clone | 05:25 |
| olofk | Remove the [provider] section, and voila, you have made your first fusesoc core :) | 05:26 |
| olofk | Now, there are a few ways to make this core override the one in the standard library | 05:26 |
| olofk | The easiest way is to launch with 'fusesoc --cores-root=/path/to/your/mor1kx ...' | 05:27 |
| olofk | If you don't want to write this everytime, you can create a fusesoc.conf in your working directory | 05:27 |
| olofk | You can start by copying the one from ~/.config/fusesoc/fusesoc.conf | 05:28 |
| olofk | And then add the path to your local core(s) after the standard library in the cores_root parameter there | 05:28 |
| olofk | Paths are separated by space | 05:28 |
| SMDwrk | ok, thanks | 05:29 |
| SMDwrk | And a result of $display() should be visible with other output of fusesoc, right? | 05:29 |
| olofk | Yes | 05:29 |
| SMDwrk | Ok, great! | 05:31 |
| SMDwrk | And what do you think about printing total cycle count information after simulation ends? | 05:31 |
| olofk | SMDwrk: If you run with --trace_enable, you will get some instruction trace files in build/mor1kx-generic/sim-icarus. Would that be what you're looking for? | 05:32 |
| SMDwrk | yep, that's it, thanks! | 05:35 |
| olofk | SMDwrk: Excellent. So you're on track then? | 05:37 |
| SMDwrk | Seems so, thanks! Now I estimate check perf impact of new branch predictor. Should I post results anywhere? | 05:38 |
| olofk | SMDwrk: Just put it on some paste service if you want us to look at them. If the predictor is added, I would guess that we want to put some kind of results in the mor1kx documentation | 05:42 |
| SMDwrk | I think it could be nice to have sort of blog/issue tracker to post openrisc related info there | 05:44 |
| olofk | We used to put these things on the OpenCores wiki, but for now, perhaps just open an issue on the mor1kx github site | 05:45 |
| SMDwrk | Ok, thanks. Speaking of my patch - it works wrong, need to fix it. | 05:50 |
| wallento | olofk: verilator 3.884 released with the olof-feature! | 08:20 |
| SMDwrk | I'm bit confused: in mor1kx do we have decode -> decode-execute -> execute -> execute-ctrl -> ctrl thing? | 09:30 |
| SMDwrk | And decode-execute/execute-ctrl store information by clk edge? | 09:30 |
| SMDwrk | So on simple recursive fibonacci c program with -O0 option I got: 5271 mispredicts with original predictor and 4192 with mine, total cond branches executed - 9482 | 11:01 |
| SMDwrk | But compiling it with -O2 gives ~66% hitrate with old predictor and ~50% on new ._. | 11:40 |
| SMDwrk | http://pastebin.com/Js7KJcJ2 | 12:36 |
| wallento | thats the weird thing about branch prediction :) | 13:51 |
| SMDhome | wallento: I think I need to take a look at asm generated and try to figure out why it happens | 13:54 |
| SMDhome | and we definitely need a scheme of mor1kx, it's too complicated for a newbie to figure out what's going on there and which wire is which | 13:56 |
| -!- Netsplit *.net <-> *.split quits: jeremybennett, olofk, nurelin | 14:26 | |
| -!- Netsplit over, joins: olofk, nurelin, jeremybennett | 14:27 | |
| olofk | wallento: Ahh.. cool. Time to build a new verilator then :) | 15:16 |
| olofk | SMDhome: Yeah, a block diagram would be great. Not sure how much work it would be though | 15:16 |
| SMDnote | I hope some tool would build it for me :3 | 15:17 |
| olofk | SMDnote: Yeah, let me know when you find that tool. I want it too :) | 15:28 |
| SMDnote | I'm looking for it for about a year now, some people suggest ice/quartus and use its rtl scheme | 15:34 |
| SMDnote | maybe not such a bad idea if it preserves all signal names | 15:35 |
| olofk | Yeah, I'm often using the RTL schema to check that things are synthesized the way I intended, but it can of course be very messy for complex designs | 15:37 |
| SMDnote | I'd like something rather simple with main blocks and interconnections between them | 15:44 |
| SMDnote | and I want to see at what clock what changes | 15:45 |
| --- Log closed Fri May 20 00:00:14 2016 | ||
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