| --- Log opened Wed Apr 06 00:00:08 2016 | ||
| olofk | Ah.. fixed the or1200-generic problems. Hope I will never have to touch that again | 02:39 |
|---|---|---|
| olofk | Anyone with the sockit board? stekern? | 04:01 |
| stekern | mmm? | 04:02 |
| olofk | sockit is the last user of the ram_wb component. I'd like to replace that with wb_ram | 04:21 |
| olofk | But I don't have my board, so I can't check it | 04:21 |
| olofk | And I'm not really sure what it's used for. It says internal SRAM | 04:22 |
| olofk | Hmm... does icarus support DPI? Anyone tried? | 04:30 |
| olofk | Doesn't like like it :/ | 04:38 |
| stekern | I think I just used it before I got the DDR working, to debug the DDR | 04:39 |
| olofk | stekern: Oh, so if I replace it with a wb_ram component it probably won't matter since it's not really used anyway :) | 04:45 |
| olofk | Nice. Running dpi with modelsim was easy | 04:47 |
| stekern | olofk: right | 04:49 |
| olofk | stekern: I'lll just do it then, so I can retire ram_wb | 04:57 |
| wallento | olofk: I also did some SRAM and DPI stuff | 05:00 |
| wallento | but more related to verilator | 05:01 |
| wallento | its a variation of what I did also for OpTiMSoC: https://github.com/optimsoc/sources/blob/master/tbench/dm/system_2x2_cccc/tb_system_2x2_cccc.cpp | 05:01 |
| wallento | I combined it with the verilator support stuff in orpsoc-cores | 05:02 |
| wallento | I will push it later today I hope | 05:02 |
| wallento | It allows to set the memory file as a parameter: --meminit=<binfile> | 05:05 |
| wallento | https://github.com/optimsoc/sources/blob/master/src/soc/hw/sram/verilog/sram_sp_impl_plain.v#L121 | 05:05 |
| wallento | the parameter changed to string recently: https://github.com/wallento/verilator/commit/c5332de86d02917b5a447ecef1328de6a07c7904 | 05:06 |
| olofk | wallento: Why do you need a DPI task for that? | 05:14 |
| olofk | I just do it by setting the mermory. Works for all simulators | 05:15 |
| olofk | For example https://github.com/openrisc/orpsoc-cores/blob/master/systems/mor1kx-generic/bench/verilator/tb.cpp#L89 | 05:16 |
| wallento | because thats the recommended way | 05:19 |
| wallento | the memory is not guaranteed to be accessible without DPI, right? | 05:19 |
| wallento | like in verilator you need to put a verilator_public to it | 05:20 |
| wallento | https://github.com/openrisc/orpsoc-cores/blob/master/cores/wb_ram/rtl/verilog/wb_ram_generic.v#L12 | 05:22 |
| wallento | the mem variable may also accessible in other simulators, but there is nothing that prevents a compiled simulation to make it inaccessible | 05:23 |
| olofk | Hmm.. I see your point | 05:25 |
| olofk | I think it should be ok anyway since we always access it in the other sims, so it can't be optimized away, but there's always a risk for that | 05:25 |
| wallento | yeah, it should be okay generally | 05:26 |
| wallento | I would only expect VCS or so to do anything to it | 05:26 |
| wallento | how do you do it in modelsim? | 05:26 |
| wallento | or icarus? | 05:26 |
| wallento | I have actually never tested it with anything but verilator | 05:27 |
| olofk | tested what? | 05:31 |
| olofk | DPI? | 05:31 |
| olofk | or do you mean access memory? | 05:32 |
| wallento | access the memory | 05:34 |
| olofk | Like this https://github.com/openrisc/orpsoc-cores/blob/master/systems/mor1kx-generic/bench/verilog/orpsoc_tb.v#L46 | 05:36 |
| olofk | Using the elf-loader in this case | 05:36 |
| wallento | I see | 05:53 |
| wallento | that should also work in any case as DPI | 05:53 |
| wallento | but the DPI solution is a bit more flexible | 05:54 |
| wallento | it can initialize any number of RAM instances | 05:54 |
| wallento | just by their name | 05:55 |
| wallento | with an SV-wrapper it always needs to be adapted to the system | 05:55 |
| wallento | but I will need to test it with modelsim, xsim and icarus | 05:55 |
| wallento | https://github.com/optimsoc/sources/blob/master/src/host/sim/src/VerilatedControl.cpp#L66 | 05:56 |
| wallento | thats where I initialize all memories | 05:56 |
| shorne | Hi all, I spent some time reviewing and testing my patch for memblock. I think its ok I just sent a mail to the list | 06:13 |
| shorne | let me know if there are any questions | 06:13 |
| shorne | Same is available here https://github.com/stffrdhrn/linux/tree/openrisc | 06:14 |
| olofk | Anyone with a riscv64 tc, who can compile some stuff for me? | 12:16 |
| olofk | wallento: Would it be hard to set up automatic build of the riscv toolchains too? Don't have time or diskspace for more toolchains on my laptop | 12:54 |
| mafm | olofk: I can give it a tri, if it's a relatively uninvolved thing to get compiled | 14:43 |
| mafm | try* even | 14:43 |
| wallento | olofk: I actually stopped jenkins and trigger builds manually on my server now | 17:01 |
| wallento | I can build one and upload somewhere | 17:01 |
| olofk | wallento: That would be nice | 17:23 |
| olofk | In the meantime, I'm looking to create riscv.bin as described here https://github.com/terpstra/opa/blob/master/demo/build.sh | 17:24 |
| olofk | Don't need the lm32 version though | 17:24 |
| olofk | Started looking at the toolchain build instructions for riscv | 17:24 |
| olofk | They propose installing the toolchain to a subdirectory of the build directory. Isn't that a bit fucked up? | 17:25 |
| olofk | or maybe not. It makes a bit sense for single user systems | 17:26 |
| wallento | yeah, its kind of developer centric | 17:32 |
| olofk | I just want to be able to compile a simple riscv program | 17:34 |
| olofk | Already have the 32-bit tc installed | 17:34 |
| olofk | How does llvm work btw? Do you only need one clang for all arches? | 17:44 |
| olofk | ok, got it installed myself | 17:53 |
| --- Log closed Thu Apr 07 00:00:10 2016 | ||
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