IRC logs for #openrisc Friday, 2016-02-05

--- Log opened Fri Feb 05 00:00:17 2016
maxpalnhowdy all! been offline for a while - mixture of illness (darn 1 year olds!), injury (one handed typing is not easy!) and house move! Hope all is well - I heard an interesting comment from our factory about Risc-V. It seems we have started an internal development for an embedded uP based on the instruction set....12:36
maxpalnI was looking at the floating point unit that is now part of the github repository for the MOR1KX. I have a need for a standalone floating point unit - i.e. not part of a uP implementation. This looks like it could be a good fit. Does anyone know of any caveats/problems using it in this way?12:52
-!- sandeep is now known as Guest2101817:45
bandvigToday I've won my laziness, and opened WISHBONE spec to find answer on my yesterday question to be 100% sure. Rule 3.45 is the answer:19:33
bandvig"If a SLAVE supports the [ERR_O] or [RTY_O] signals, then the SLAVE MUST NOT assert more than one of the following signals at any time: [ACK_O], [ERR_O] or [RTY_O]."19:34
olofkmaxpaln: Yeah, Lattice is an official RISC-V sponsor now, so that makes sense19:45
--- Log closed Sat Feb 06 00:00:19 2016

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