IRC logs for #openrisc Thursday, 2015-12-31

--- Log opened Thu Dec 31 00:00:26 2015
mor1kx[mor1kx] bandvig pushed 1 new commit to marocchino_devel:
mor1kxmor1kx/marocchino_devel 6fafd3d Andrey Bacherov: Happy 2016 Year Release. The major achievement is that all modules, including LSU, DCACHE, Store Buffer, etc. are ready for more pipelinization. All RAM blocks are replaced with ones containing "enable" signal. And Read/Write conflict resolving is moved out from RAM modules. Both of these modifications are essential steps toward design of pipeline control logic for each pipelined module.10:42
-!- Dan_ is now known as Guest6728819:39
--- Log closed Fri Jan 01 00:00:27 2016

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