IRC logs for #openrisc Friday, 2015-11-20

--- Log opened Fri Nov 20 00:00:17 2015
andrzejr_I am seeing error with 8-bit (only) ram access initiated by openocd. Memory access via a test program on CPU (cache off) or via gdb 'x' command works fine.03:52
andrzejr_gdb read access (correct):03:52
andrzejr_(gdb) x/32xw 0x0000100003:52
andrzejr_0x1000:0x000102030x040506070x08090a0b0x0c0d0e0f03:52
andrzejr_(gdb) x/32xh 0x0000100003:52
andrzejr_0x1000:0x00010x02030x04050x06070x08090x0a0b0x0c0d0x0e0f03:52
andrzejr_(gdb) x/32xb 0x0000100003:53
andrzejr_0x1000:0x000x010x020x030x040x050x060x0703:53
andrzejr_and the same memory contents read using openocd commands (mdw, mdh, mdb):03:54
andrzejr_0x00001000: 00010203 04050607 08090a0b 0c0d0e0f 10111213 14151617 18191a1b 1c1d1e1f03:54
andrzejr_0x00001000: 0001 0203 0405 0607 0809 0a0b 0c0d 0e0f 1011 1213 1415 1617 1819 1a1b 1c1d 1e1f03:54
andrzejr_0x00001000: 00 01 02 02 04 05 05 07 08 08 0a 0b 0b 0d 0e 0e 10 11 11 13 14 14 16 16 18 19 1a 1a 1c 1d 1d 1f03:54
andrzejr_0x00001000: 00 01 01 03 04 04 06 06 08 09 0a 0a 0c 0c 0e 0f 10 10 12 12 14 15 16 16 18 19 19 1b 1b 1d 1e 1f03:55
andrzejr_Note the last two lines (byte access) are incorrect and errors are random.03:56
andrzejr_does gdb's 'x' command access memory via cpu? (not dbg_if wb master?) If so, are there any differences in the way both masters (mor1kx and dbg_if) access wb bus?04:00
olofkandrzejr_: That's very interesting11:44
olofkI don't have a clue about the internals unfortunately :/11:44
_franck__andrzejr_: both methods use target_read_memory at the end so it always use dbg_if wb master16:09
_franck__could you run both tests with -d 3 on openocd cmd line ?16:09
andrzejr__franck_, gdb performs multiple reads: or1k_du_adv.c:450 adbg_wb_burst_read(): Doing burst read, word size 1, word count 1, start address 0x0000100021:40
andrzejr_openocd's mdb command reads everything in a single burst: or1k_du_adv.c:450 adbg_wb_burst_read(): Doing burst read, word size 1, word count 32, start address 0x0000100021:41
andrzejr_During bursts, wb spec requires the address has to increment in steps of 4 bytes, so how can dbg_if wb master do burst reads of single bytes?21:59
--- Log closed Sat Nov 21 00:00:18 2015

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