--- Log opened Mon Nov 16 00:00:11 2015 | ||
-!- trevorman_ is now known as trevorman | 07:15 | |
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-!- Empyrium_ is now known as Empyrium | 07:32 | |
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olofk | hesham: I made some fixes to mor1kx-generic and would like to do the same fixes to vscale-generic | 13:00 |
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olofk | I added a simulation mode to uart16550 and dropped the uart16550_model | 13:01 |
olofk | _franck__: Would be great if you could try to bump wb_intercon to wb_intercon-1.0 for neek and de1 | 13:04 |
olofk | stekern_: Same thing with sockit | 13:04 |
_franck__ | olofk: why wb_intercon is in orpsoc-cores and wb_intercon-1.0 on your github ? | 13:07 |
olofk | _franck__: Because I've been trying to move RTL code out from orpsoc-cores | 13:20 |
olofk | So it's only old ones that are still in orpsoc-cores | 13:20 |
_franck__ | ah ok. However, if you move everything out of orpsoc-cores you may loose the ability to maintain some cores where the owner is not available anymore | 13:30 |
olofk | _franck__: Yes, I guess that's the same thing for all Linux distributions as well :) | 13:39 |
olofk | But we can always clone the repos | 13:39 |
olofk | And I have also started to use specific revisions for most cores, so that we don't get affected if the git HEAD changes | 13:40 |
olofk | For example, I have already cloned the uart16550 repo and applied patches there, so we're no longer using the one from opencores | 13:40 |
hesham | olofk: done | 13:47 |
hesham | It's also slower than the previous uart model module | 13:49 |
olofk | hmm... | 13:59 |
olofk | Did you set the SIM parameter? | 13:59 |
olofk | I thought I had hacked it to be as fast as it could be, but I probably missed something | 14:00 |
hesham | olofk: Setting it on has no notable effect | 14:03 |
olofk | hmm.. | 14:03 |
hesham | I wouldn't worry about how quick/slow it's as long as it's working correctly though. | 14:05 |
olofk | No, it's not that important, but I thought I had made it as quick as the model, so I was a bit suprised | 14:06 |
hesham | Don't you have the same behaviour? | 14:09 |
olofk | Actually, I realized that I haven't really been using the uart model. Most of my tests were using elf files that used the l.nop 0x3 feature to write to stdout | 14:11 |
olofk | Is it much slower? | 14:11 |
olofk | Looking at the code, I would suspect it's about four times slower | 14:11 |
hesham | It's printing out characters with some notable delay | 14:12 |
hesham | Few milliseconds or so, but can be noticed. | 14:12 |
hesham | That wasn't the case with the UART model module. | 14:13 |
olofk | I'll try to fix that, but if it's ok I'm pulling your patch now, because I want to retire some old code in orpsoc_cores | 14:21 |
hesham | That's fine | 14:25 |
olofk | hesham: Fixed the UART issue now. Pushing some updates | 14:48 |
hesham | olofk: Great, let me know when you push the updates to give it a test. | 14:49 |
olofk | pushed | 14:50 |
hesham | olofk: I'm afraid it's still slow. | 14:59 |
olofk | Did you set SIM? | 14:59 |
olofk | It was much faster for me | 14:59 |
hesham | Yes | 15:00 |
olofk | hmm.. | 15:00 |
hesham | UART_SIM | 15:00 |
olofk | yep | 15:00 |
hesham | Not sure what's wrong | 15:00 |
olofk | Me neither | 15:00 |
olofk | hmm.. you're right | 15:03 |
olofk | It's no big difference here | 15:03 |
olofk | For mor1kx-generic it was a huge difference | 15:04 |
hesham | So you tested the vscale one? | 15:06 |
hesham | Maybe it's the way the code is written? | 15:06 |
hesham | I don't think so, it's just one line ... | 15:07 |
hesham | *((volatile char *)0x90000000) = c; | 15:07 |
hesham | It doesn't even poll on LSR | 15:07 |
olofk | Yes. That's probably why it isn't faster on vscale with the latest fix | 15:11 |
olofk | The elf I was using for mor1kx-generic polled lsr, so it was really slow | 15:11 |
olofk | ok, so we're still a bit slower than the model, but I don't think I'll spend more effort on that now. It shouldn't be too much difference | 15:11 |
hesham | But the RISC-V elf is not polling on LSR. | 15:12 |
hesham | I agree, it's not a big issue. | 15:12 |
olofk | It might also be that I'm flushing now after each character so it might be that it just appears slower | 15:13 |
olofk | Because every byte is written out one by one | 15:13 |
hesham | ** With Hello World at least | 15:14 |
hesham | Was it buffered with the uart model? | 15:14 |
olofk | Looks like that | 15:16 |
olofk | You could try to comment out the $fflush in uart_transmitter.v and see if it helps | 15:16 |
olofk | You'll find it in ~/.cache/fusesoc/uart16550-1.5.2/rtl/verilog (if you used the default directories) | 15:17 |
hesham | olofk: Yes it doesn't introduce delays between characters, but it does between lines | 15:18 |
hesham | And it doesn't output anything if there's "Hello World" without \n | 15:20 |
hesham | So I think it buffers it until it find "\n" | 15:20 |
olofk | ah ok. Maybe I should remove the fflush then | 15:21 |
olofk | But I think the speed should be almost as fast as the model now | 15:21 |
hesham | It's now the same as before when commenting fflush | 15:21 |
hesham | before == uart model | 15:22 |
hesham | But still the delay exists between lines. | 15:22 |
olofk | Was there a delay between the lines with the model? | 15:23 |
hesham | I can't give an answer for that as I didn't use multi-line output program with the uart model | 15:26 |
hesham | Let me reset and see | 15:26 |
hesham | Yes it's there! | 15:27 |
hesham | I think that's expected, giving that it's cycle accurate. | 15:29 |
-!- clopez_ is now known as clopez | 17:58 | |
-!- mboehnert1 is now known as mboehnert | 19:58 | |
olofk | Alright. I'm about to release a new FuseSoC version now. | 21:18 |
olofk | Anyone good with autotools? | 21:35 |
olofk | https://github.com/olofk/fusesoc/releases/download/1.3/fusesoc-1.3.tar.gz | 22:16 |
olofk | Hello github releases. Goodbye opencores FTP | 22:17 |
--- Log closed Mon Nov 16 23:00:39 2015 | ||
--- Log opened Mon Nov 16 23:00:56 2015 | ||
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--- Log closed Tue Nov 17 00:00:13 2015 |
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