IRC logs for #openrisc Wednesday, 2015-10-21

--- Log opened Wed Oct 21 00:00:35 2015
-!- orsonmmz|away is now known as orsonmmz02:34
olofkGeneralStupid: Can't find anything obvious there either :/04:59
olofkGeneralStupid: You could add a LED blinker to your top-level to ensure that clocks and reset is working properly05:10
_franck_andrzejr: good to hear05:31
stekernfwiw, should work without atomic instruction support06:06
stekernit has emulation in the kernel for them06:06
andrzejr_franck_, the results are very confusing, though. It looks like my wrapper produces correct DDR ctrl read requests but gets data from wrong places in the memory.07:38
olofkandrzejr: Could it be wrong CAS/RAS latency?11:00
andrzejr_olofk, will check that. it sounds plausible, especially that digilent used a "Micron-compatible" part11:52
* olofk hates DDR* memory interfaces13:04
olofkI still wonder why not high speed serial links are used more for memories. Sure, you get a higher latency, but it would surely be cheaper to smack on a SERDES instead of routing millions of parallell high speed pins13:06
olofkAnd I guess that memories are mostly read and written in blocks nowadays, so for larger block sizes, the latency will be less critical13:07
olofkI know there's HMC (Hybrid Memory Cubes) that uses serial links, but if I have understood this correctly, they are on-chip, or even on-die memories13:08
poke53281Sooner or later you might no longer have external memory modules, but stacked RAM instead.13:08
poke53281Yes, on-die memories13:09
olofkoh.. there's something called gigachip13:12
olofkCan't find any compatible memories though :)13:14
juliusb_hey guys, did we get the ORCONF group photo posted anywhere yet?13:16
poke53281olofk: Is there a problem with the low and high flank during a clock pulse when you try to access DDR? Wonder If you can take of this feature when you program an interface.13:43
poke53281I mean rising edge and falling edge13:43
olofkjuliusb_: Don't think so, but I got them if you want them. simoncook sent them over16:06
olofkpoke53281: Not sure I understand what you mean16:07
juliusb_olofk: ah cool. should we put it up on the site?16:08
olofkjuliusb_: Sure thing16:12
GeneralStupidHi Guys17:05
GeneralStupidolofk: where is the program counter - counter? :-D17:05
olofkGeneralStupid: pc something. You could for example try traceport_exec_pc_o or pc_execute_to_ctrl17:19
andrzejr_olofk, ddr5 is going in this direction - no multi-drop buses, higher bitrates etc17:47
robtaylorolofk: latency, and the fact that buying HMC is like buying gold dust ;)17:50
robtaylorstacked DRAM is hard due to heat issues17:51
andrzejr_but dram process is simply not good enough (cost!) for high speed series or low noise vco designs. few (and thin) metal layers and rubbish transistors lacking most speed optimisations17:51
robtaylore.g. SpiNNacker has in-package DRAM, but it comes in at <1W17:52
robtaylorandrzejr_: yeah, hence HMC using TSVs17:52
robtaylorbut TSVs are way too low yeld and expensive at the moment, as I understand it17:53
andrzejr_yes, plus you don't just drill holes worth 1M transistors each in RAM. electrically they are not very different from other series channels17:56
andrzejr_eh, autocorrection18:00
robtaylorandrzejr_: heh18:05
robtaylorthe folk i know that have played with HMC have said the latency is too high though18:05
andrzejr_afaik in HMC you talk to a (fast) proxy chip which then forwards requests to dram chips. good for bandwidth, not so for latency18:09
andrzejr_also, not sure if stacking is cheaper than extending dram process18:10
robtaylorandrzejr_: yep18:22
robtaylorvagyely related
robtaylorolofk: good overall refernce in this
olofkok, I hadn't considered that DRAM processes were a bad match for high speed serial designs20:54
olofkBut the proxy chip design sounds interesting. If latency or even bandwidth ain't critical you could save a lot of PCB area if you had a discrete DDR+SERDES IC. Still feels like that would make sense in a lot of applications20:57
olofkah ok.. so HMC _is_ chip to chip, but they use TSV between the DRAM and the controller21:11
andrzejrit looks like it wasn't CAS latency, checking other timing parameters21:24
andrzejrstekern, I have pushed a small fix to diila's waveform generator:
andrzejrit filters out unnecessary transitions so that the waveforms look more readable in gtkwave23:59
--- Log closed Thu Oct 22 00:00:36 2015

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