IRC logs for #openrisc Tuesday, 2015-09-29

--- Log opened Tue Sep 29 00:00:04 2015
andrzejr_strange, enabling caching is very fragile (in HW) but once I've managed to do the memory works just fine.00:07
-!- orsonmmz|away is now known as orsonmmz07:41
maxpalnstekern: aha - as long as they are known failures that is ok with me. It looks like I now have my known good starting point!09:12
maxpalnIn case anyone needs this in the future, I wrote down all the steps I followed to get to this point from my vanilla windows 8 machine - i.e. from the point of downloading VirtualBox and installing Ubuntu. It is here:
-!- yang_ is now known as yang11:14
-!- antgreen` is now known as antgreen12:21
maxpalnolofk: just reading back over our conversations on the irc logs and saw this from you a few days ago:12:55
maxpaln"Hey, that's cheating! Everyone is supposed to keep the instructions in their heads. No guides are allowed"12:55
maxpalnI guess actually reading the IRC logs already broke that rule - writing everything down is probably enough to get me disbarred :-)12:56
maxpaln[thinks to self: maybe that's why no one is replying...14:21
stekernwe're all busy watching little britain15:11
maxpalnI'm new to icarus so I'm not really sure how to solve this problem - for other simulators you can have a technology library (a precompiled list of files that contain primitives like OR gates and so on) - for Verilog libraries they get referenced via -L options to the simulator command usually. Does the same capability exist for icarus? If so, where are the libraries stored?15:48
maxpalnlooking at the documentation the closest would be to reference the directory containing the primitives as a -Y option. Straight forward enough but I am not sure fusesoc has a place in the .core file for library directories. I can't see it in the examples so far...15:53
andrzejr_maxpaln, fusesoc's icarus backend doesn't use the -Y option. It simply writes all source files to icarus.scr and starts iverilog with -c icarus.scr18:57
andrzejr_you can add some libraries manually via <core>.core file, e.g.:18:59
andrzejr_iverilog_options = -DICARUS_SIM -DSIM -y /opt/Xilinx/14.7/ISE_DS/ISE/verilog/src -y /opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/unisims18:59
-!- orsonmmz is now known as orsonmmz|away19:20
olofkmaxpaln: These are good instructions to have around. Might clean up and put on a website if you don't mind19:44
olofkandrzejr_, maxpaln: FuseSoC now allows environment variables in the .core file, so you should hopefully be able to do $XILINX/verilog/src to make it a bit less dependant on installation directories19:46
andrzejr_I spent several hours setting up simulation (xsim, with ddr2 model and no elf-loader etc) trying to replicate an "issue" with enabling the cache in HW. The symptom I was seeing in HW was that the program appeared to be stuck in _cache_init22:05
andrzejr_it turned out that the test runs succesfully but there is no any halt or loop at the end, so it continues to the next portion of the program, which is happens to be _cache_init :-)22:07
andrzejr_is or1k-tests even meant to be used in HW? it would be good to have success&fail subroutines which e.g. light an LED22:08
andrzejr_olofk, so everything I was writing about cache *yesterday* is invalid. So far, cache works just fine in simulation and hardware.22:10
andrzejr_The issue with 128b cache line size is different and is real, I think.22:11
-!- mboehnert1 is now known as mboehnert23:32
--- Log closed Wed Sep 30 00:00:05 2015

Generated by 2.15.2 by Marius Gedminas - find it at!