| --- Log opened Fri Aug 21 00:00:09 2015 | ||
| olofk | I told you the Atlys DVI error was random :) | 06:10 |
|---|---|---|
| andrzejr | olofk, there was also something fishy about eth timing - very different in both runs (with violations in the failing one). | 07:51 |
| andrzejr | On the plus side, I have managed to get the DDR2 i/f to calibrate the link. I didn't notice there were some options for enabling/speeding it up in simulation. | 07:52 |
| andrzejr | I have the memory model and the DRAM i/f as separate cores. I wonder if it is good idea to push them to the repo. | 07:53 |
| andrzejr | DDR2 DRAM model downloads itself from the web so I guess this is OK, but I am not sure what are the licensing terms for distributing the Xilinx MIG DDR i/f. Apparently it can be distributed to people who have the ISE license. | 07:56 |
| olofk | andrzejr: Good to hear. I've heard other people talking about the eth timing too. There is probably something weird there, but I haven't investigated it too much | 08:40 |
| olofk | One thing to notice is that if you get hold time violations, it can be an indication that something is badly constrained in another part of the design so that ISE spends a lot of effort trying to meet some timing that it really shouldn't try to meet | 08:41 |
| olofk | My first suspect would be an unhandled CDC. Perhaps the reset signal. I know also that there is some fishy CDC in the FIFO as well. Been meaning to investigate that, but haven't found the time to do so | 08:43 |
| olofk | I understand your concern about the MIG stuff. The idea has always been to just distribute the xco and cgp files and let FuseSoC call coregen to regenerate it on the fly, but once again, I haven't had time to implement that properly :) | 08:44 |
| olofk | I don't think Xilinx will come after you for distributing the MIG code, but if you are concerned, you could try to make a script that generates it and add it to 'pre_build_scripts' in the .core file | 08:45 |
| olofk | andrzejr: You're an XFCE dev as well? | 08:51 |
| olofk | I mean as well as an RTL hacker | 08:51 |
| -!- Netsplit *.net <-> *.split quits: rokka | 12:39 | |
| -!- Netsplit over, joins: rokka | 12:49 | |
| --- Log closed Sat Aug 22 00:00:10 2015 | ||
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