IRC logs for #openrisc Tuesday, 2015-08-18

--- Log opened Tue Aug 18 00:00:05 2015
latifhi all.. As I told you before I am trying to boot orpsocv3 from spi flash on atlys board..11:46
latifI have added a led blink app to bootrom.S code to understand whether it is working correctly..11:47
latifThe result is not positive.. Niether orpsocv2 nor orpsocv3 could not run it. I mean the booting is successfull but the leds are not blinkjing.. Before, I managed to run such app by using a C code (then turning it to a mcs file) on orpsocv2 (not on orpsoc v3- tried but not managed to run)..11:50
latifSo I think there may be a pproblem with bootrom.S11:51
latifor it is a problem related with atlys board11:51
_franck__latif: is your boot address correct ?12:34
_franck__.OPTION_RESET_PC (32'hf0000100)12:34
latifI think so.. because I have managed to boot orpsocv2 before12:35
_franck__does it match what's in wb_intercon.conf in rom section ?12:35
_franck__ah sorry you are using an existing system so it should be correct12:36
latifyes.. It should be.. because I did not change anything on rom.v or wb_intercon.conf.. Just added the bootrom code into the rom.v12:38
_franck__where did you edit the rom.v file ? because it is maybe overwritten while building with fusesoc12:39
_franck__to be sure put some garbage in the file you edited to see if Xilinx complains12:40
latiffranck... I have tried it before.. I get a xilinix project and add it all files. Xilinix complains if you do anything wrong..12:47
_franck__I didn't mean you open the Xilinx project, just do "fusesoc build atlys"12:49
_franck__to see if you're compiling with your midification included12:49
latifAha.. I see.. But the answer is still yes.. I mean for example if you change a module (add a stupid thing in it) and run "fusesoc build atlys" then Xilinxs complains you about that12:55
_franck__" booting is successfull" -> how do you know that ?12:56
latifFRANCK...when I power on th board after loadin mcs, a done led on board is blinking after 3-4 seconds.. like the other succesfull triyings..13:04
_franck__I guess done means "FPGA configured" (who's blinking this led ?) it doesn't mean the CPU start executing the code in the rom13:11
latif_franck_... yes you are rigth.. I can not say it as an evidince..13:20
blueCmdstekern: do you have any synthesis statistics on mor1kx on your Zynq?14:22
blueCmdhow much did it use etc14:22
blueCmdI'm considering buying something with a Zynq Z-7020 in it, but I have no sense of how big the FPGA is14:22
-!- Netsplit *.net <-> *.split quits: _franck_, bentley`, jeremybennett, hansfbaier14:59
-!- Netsplit over, joins: hansfbaier, jeremybennett15:12
stekernblueCmd: sorry no, I've never got around to play with mor1kx on the zynq15:27
andrzejrblueCmd, it will fit easily18:10
blueCmdandrzejr: right, but what more? I'm trying to get an estimate of how "big" that version is18:11
andrzejr7020 has 85k logic cells, I'm currently using Artix7 (same fabric) with 100k cells and the whole orpsoc with capuccino and DDR2 i/f (the biggest contributor) takes ~20%.18:11
blueCmdI have a Kintex that's like *gigantic*, 64 OpenRISCs without a problem :P18:11
blueCmdCool, thanks!18:11
andrzejrMor1kx itself takes 1499 slices (out of 15860) and 15 BRAM blocks (~9%). Zynq is only slightly smaller.18:21
andrzejrolofk, how to do cdc with buses?22:08
andrzejrI have two synchronous (fixed phase offset) clocks: wb_clk and ui_clk (generated by dram i/f) - synthesis is fine, simulation in most cases too, so it looks like the autogenerated timing constraints are OK22:10
andrzejrbut in one case the simulation enters a combinational loop, not sure if that's because of my error or if making such cdc is a bad idea22:11
andrzejrfor obvious reasons I want to avoid asynchronous cdc22:12
andrzejrsorry, the error is caused by something else22:23
--- Log closed Wed Aug 19 00:00:06 2015

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