IRC logs for #openrisc Wednesday, 2015-08-05

--- Log opened Wed Aug 05 00:00:46 2015
andrzejrlooks like icarus verilog does not compile a (new) mig generated ddr2 controller00:16
andrzejrI tried adding a -g2005 option - no difference. Any ideas?00:17
andrzejrbtw, what is this syntax:00:18
andrzejr(* full_case, parallel_case *) case (init_state_r)00:18
andrzejriverilog from git has some of the errors fixed, I have worked around other syntax errors (reported upstream) but ultimately arrived at a road block. MIG DDR2 interface requires some encrypted modules (for selected simulators), which means there is no chance of making this code simulate in iverilog. bummer02:09
andrzejrall encrypted components are related to Phy and Serdes primitives so even if we managed to write our own DDR2 interface we would have to depend on them.02:13
_franck__andrzejr: I think Altera has some simulation models for their encrypted files I don't know about Xilinx07:32
andrzejr_franck_, but those _are_ simulation models. Do you mean some simplified models?07:50
_franck__an encrypted version of the file for synthesis and another version of the file (not encrypted, may be simplified) for simulation07:56
andrzejrUnfortunately Xilinx went step further and encrypts also simulation models. They support (encrypt for) several commercial simulator but that won't work for iverilog.08:04
andrzejrdo you know if this is also the case in series-6 and older devices (e.g. Spartan 6)?08:06
stekernandrzejr: yes, it's also true for spartan608:46
jagadeeshadding additional gpio pins to fusesoc de0_nano system10:43
jagadeeshAny one out there have got this working10:43
jagadeeshI tried editing wb_intercon.conf and pin configuration. no luck yet10:45
_franck__jagadeesh1: did you add a new gpio controller in your top file ?11:36
jagadeesh1okay my mistake11:38
_franck__what do you want to do ?11:38
jagadeesh1add additional gpio pins to the system de0_nano11:38
_franck__ok so add a new gpio controller, edit wb_intercon.conf and re-generate the interconnect files with wb_intercon_gen11:40
_franck__I forgot you need to add pins in pinmap.tcl11:40
jagadeesh1thank you frank can u please tel me where can i get a good guide to use openrisc11:42
jagadeesh1where did you learn all these11:42
_franck__well, I'm working with operisc for quite some time so I learned while trying to make thing works11:48
_franck__(as usual)11:48
_franck__look here for a tutorial:
jagadeesh1thank you frank.11:49
ErikZDoes anyone have some info on how the wishbone bus behaves when writing and reading to a byte segmentet 32 bit bus?14:20
ErikZAFAICT, When writing 8 bits to the bus it looks like for accessing the 4 different bytes of a 32 bit word the address is kept at the low base and the sel_i is toggled14:22
ErikZIf i want to write byte 1 (ordered from 0 and up) of address 0. adr_i is kept at 0 and sel_i is set to 0b0100. This is then decoded by the wishbone slave.14:24
ErikZNow I am trying to read the same byte on the wishbone bus, but for some strange reason the adr_i is not kept at the base but is instead: adr_i = 0x1, sel_i = 0b010014:27
ErikZIs there an assymetry between how the adr_i bus is toggled when writing and reading to the same byte?14:28
_franck__as stekern said :"yeah, actually, maybe it's only on stores that the lower 2 bits are masked"14:34
ErikZ_franck__: Wow, you are a star14:40
ErikZDoes the or12k exhibit the same behavior? What does the spec say?14:41
ErikZWhy not X mark bit 0 and 1 instead? Then you will catch misuse of the bus during simulation and also allow the synthesizer to optimize it.14:59
_franck__I think or12k does that too15:08
_franck__if core look at wb_sel (like they must do) having bit 0 and 1 set is not  big deal since they are supposed to be ignored15:10
_franck__I don't know if the spec tells about forcing bits [1:0] to 015:11
stekernif you perform 32-bit wishbone accesses (regardless of bytesel), bit [1:0] are don't care according to the spec16:15
GeneralStupidI have a strange question... i need a pic programmer for just one pic... do you think i could use my fpga to do that?18:49
-!- rhythmx is now known as threatbutt20:55
andrzejrwhat hdl simulators do you use with orpsoc? I see fusesoc only supports icarus verilog, modelsim and verilator. Out of these, only modelsim works with encrypted Xilinx models but the free version is only available for Windows.21:29
andrzejrHas anyone tried using isim with fusesoc?21:30
GeneralStupidiam using a free modelsim on linux...21:43
andrzejrGeneralStupid, is there any free version?21:48
GeneralStupidi think i just installed quartus there was a free version included21:50
andrzejrok, but I guess this version does not support Xilinx encrypted libraries, does it?21:51
GeneralStupidpossible, i'am sorry i dont know that ...21:52
-!- threatbutt is now known as rhythmx23:52
--- Log closed Thu Aug 06 00:00:47 2015

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