IRC logs for #openrisc Friday, 2015-07-31

--- Log opened Fri Jul 31 00:00:39 2015
ErikZHow can I push down an argument to the simulator from the cmdline using fusesoc?08:38
ErikZI want to push down "-i" to vsim08:38
GeneralStupidis anyone able to help me with the XILINX ISE?09:48
juliusbGeneralStupid: what's the issue?10:41
ndrw1I'm using ISE now with an Artix7 device - works fine. Has some problems building an atlys system. Most problems seemed to be related to constant pushing removing bits of circuit that p&r assumed they are still there.11:42
GeneralStupidjuliusb: i want to connect my xilinx device with simulink... the problem at the moment is that i can only use std_logic and std_logic_vector as in and outputs11:43
GeneralStupidbut i heavily use the fixed_pkg :)11:43
ndrw1verification, cosimulation or hw acceleration?11:52
GeneralStupidhw acceleration... :)11:53
ndrw1I'd probably bypass ISE and talk to the chip directly via JTAG or SPI. then you only need some generic drivers for matlab11:58
GeneralStupidok... these generic drivers are the tricky part for me :)11:59
ndrw1I used SPI for that, although that was more hw evaluation than acceleration.12:00
ndrw1and it was plain Matlab, not simulink12:00
GeneralStupidthats possible with matlab?12:01
GeneralStupidfor me its both, acceleration and verifying...12:01
GeneralStupidi want to know which parameters fits best and if hardware is really that big effort for this particular case...12:01
GeneralStupidat the moment we already have a very fast C implementation...12:01
GeneralStupidthat thing should be used on a hearing aid device so we need to try everything out :)12:02
ndrw1I used cheetah SPI dongle - it has drivers for many tools. on the chip side we had an SPI slave to AHB bridge so you could talk to anything visible to the cpu12:04
ndrw1also, mex compilation (fiaccel) was good enough in most cases. about 100x speedup vs normal fi code12:06
GeneralStupidour hearing aid does not have a C Compiler, so we need to rewrite in assembler :)12:07
GeneralStupidi hope my hardware implementation is good enogh, dont want that :)12:08
ndrw1no, that was a testchip with some hardcoded DSP logic that was attached to SOC bus12:08
ndrw1still not sure what you want to do - run some simulink sims with art of the design implemented in assembler on a soft core?12:11
GeneralStupidi got a matlab filter from a mathematician. I made them useful in real world... and then i "translated" it to hardware...12:12
GeneralStupidthe filter only operated on a whole audio sample... very much unusable, a lot of stuff had to be rewritten...12:12
ndrw1I did something similar. implemented a fi model (with fiaccel compilation), compared the performance against the reference design whilst still in Matlab, dumped some hex patterns for input and output, reimplemented the whole thing in RTL using the patterns as a reference.12:18
ndrw1no hw acceleration was required and that was several Mgates.12:19
ndrw1instead of test patterns you can also generate a reference RTL from simulink but I haven't tried that12:20
ndrw1have to go, ttyl12:21
olofkandrzejr: Saw your question about LGPL. The whole idea of using LGPL in this context is to be able to mix proprietary code with LGPL-licensed code21:15
olofkSo you would only have to disclose potential changes in the LGPL-licensed cores that you use.21:15
olofkI have been talking to other projects using LGPL for IP cores (such as the OHWR team at CERN) and everyone seem to be agreeing with this interpretation21:17
andrzejrolofk, I assumed this is the case. But I've never seen any such exception or interpretation included in the code.21:21
olofkandrzejr: You're right. It would probably be beneficial to have this written down somewhere21:22
andrzejrfor example Linux kernel's license explicitly say that syscalls are not treated as an extension to the kernel code.21:22
olofkjuliusb created a new license for mor1kx with basically the same properties as LPGL, but more explicitly worded for FPGA/ASIC21:22
andrzejrI have tentatively decided to use BSD license for my contributions (or public domain for trivial additions) but I like the idea of enforcing RTL modifications to be disclosed.21:24
olofkandrzejr: That's a good idea. Unfortunately we will not be able to add such a paragraph to all the code, since many of the original authors have moved on21:24
olofkI would like to see both a BSD-like license and an LGPL-like license better suited for FPGA/ASIC, but I think that the software licenses are ok until then21:26
andrzejrhow about LGPL in orpsoc? technically, attaching a proprietary IP to the SoC bus is extending the SoC.21:28
andrzejrIMHO orpsoc_top.v should not be LGPL licensed. It is only a wrapper anyway, so we do not need to be too fussy about protecting it.21:30
olofkandrzejr: Agreed. I've also been experimenting with autogenerating the top-level with IP-Xact, in which case it will probably just be public domain or something21:32
olofkI'm fine with removing licenses for top-level files that I have created21:32
olofkGoogle already removed my license in the ProjectVault repo and replaced it with their own license :)21:32
andrzejrI like the idea of OHDL, has juliusb discussed it with anyone (OSI, FSF)? It would be great to have it "blessed" by one of them.21:39
andrzejrolofk, btw, I've modified wb_data_resize.v to support 16b and mixed-size bus accesses. Works well here but I haven't checked it with other systems.21:44
andrzejrhmm.. timing violations with 133MHz wb_clk frequency and Artix7 -3 speed grade21:52
andrzejrwill have to drop it to 89MHz or 66MHz (I want wb_clk to be synchronous to the 266MHz ddr2 clock)21:54
andrzejrTiming met at 89MHz wb_clk and speed grade -2 :-)22:22
--- Log closed Sat Aug 01 00:00:40 2015

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