IRC logs for #openrisc Tuesday, 2015-07-28

--- Log opened Tue Jul 28 00:00:35 2015
ErikZwhat happens to the mor1kx cpu when it performs a wishbone access? Does it simply stall?14:47
stekern_ErikZ: depends if it's a load or a store (and if you have the store buffer enabled)14:51
-!- stekern_ is now known as stekern14:51
ErikZstekern: When you accessed flash via spi, did you ever perform any measurements on the transaction bandwidth?15:08
andrzejrI have pushed some fixes to orpsoc-cores:
andrzejrstekern, this^ includes a fix (hopefully) for 8/16/32b access and support for 16b slaves.18:08
andrzejr8b(access)<->8b(slave) case should behave same as before. Newly supported combinations are: 32b(access)<->16b(slave), 16b<->16b, 8b<->16b, 32b<->8b, 16b<->8b.18:15
--- Log closed Wed Jul 29 00:00:36 2015

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