IRC logs for #openrisc Friday, 2015-07-24

--- Log opened Fri Jul 24 00:00:29 2015
stekernErikZ: that doesn't sound right04:51
stekernso is it the actual spi transactions that take that long?04:53
ErikZstekern: I haven't scoped it out yet so I am unsure what actual clk frequency the transactions run at. The driver claims it sets different frequencies depending on what max value I define in the dts file.06:38
ErikZI will try to switch to the tiny spi ip today and see if I get different results06:39
stekernErikZ: Ok, FWIW, I've tried spi->serial-flash with normal speeds in the past06:52
stekernthat would pretty much match the setup you are trying06:52
jagadeeshHi is there any tutorials for using orpsoc in a custom altera fpga board11:37
GeneralStupidjagadeesh: which board?11:39
jagadeeshActually i am going through stefan's openrisc port for de0 nano board. I would learn how can i build a new systems of openrisc soc with different peripherals11:41
_franck__jagadeesh: my advice is to start with fusesoc11:41
_franck__and you can start from one of the board supported here:
GeneralStupidit depends on which board it is... i did a implementation for the de211:42
jagadeesh_frank__: Can i customize the peripherals with fusesoc11:43
_franck__jagadeesh: yes you can. The memory map you want is defined in a script (i.e:
jagadeeshGenearlStupid: I have a de0 nano, can u show me some links where i can find a way to start from scratch with de0 nano board.11:45
_franck__then you can generate the interconnect automatically11:45
jagadeeshthank you _frank__ :). I will try with that.11:46
GeneralStupid_franck__: nice, is that page new?11:47
_franck__no it's not11:48
_franck__but not that old too11:48
GeneralStupidOh  :/12:08
GeneralStupidI implemented a sample_buffer and now i have A LOT OF LATCHES ...12:08
--- Log closed Sat Jul 25 00:00:30 2015

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