IRC logs for #openrisc Monday, 2015-07-20

--- Log opened Mon Jul 20 00:00:23 2015
-!- a0u is now known as aou00:13
andrzejrWhy l.lbz r4,0x0(r3) and l.lbz r4,0x3(r3) read different values into r4, even though the bus returns the same 32b value in both cases (an IO reg)?01:53
stekernandrzejr: but you are reading separate bytes from that 32b value05:34
stekernre wb_intercon 16-bit support, I bet you are the first to try actually test that, so you might have hit some bug, yes. olofk might need to confirm though.05:37
andrzejrstekern, looks like wb_data_resize is hardcoded to 8-bit slave bus width. I will look at it later but for now I have worked this around by only using 32 and 8b bus sizes.06:56
andrzejras for the l.lbz behaviour - I will check that in simulation later, still have to set it up.06:59
andrzejrbut if feels potentially wrong - what if you read location 0x3(r3) from memory? IMHO CPU should issue a misaligned address and use [31:24] range (big-endian) of the result.07:03
stekernyes, or not a misaligned address but the right byte-selects set07:06
andrzejrstekern, that would indeed work for 8bit access and in fact that what I see it doing. But what about misaligned 16b and 32b access?07:12
stekernif you have *r3 = 0x12345678, you'd expect lbz r4, 0(r3) => 0x12, lbz r4, 1(r3) => 0x34, lbz r4, 2(r3) => 0x56, lbz r4, 3(r3) => 0x78, right?07:14
stekernif you do a misaligned access, you'll get an misaligned access exception07:14
andrzejrI see, so or1k implementations don't support misaligned accesses in HW and fall back to SW via exceptions? That makes sense and is a lot easier on HW side, I just didn't know about it.07:19
andrzejrOK, then one less thing to worry about, then. Thank you.07:22
-!- mboehnert1 is now known as mboehnert14:42
-!- pecastro_ is now known as pecastro14:47
-!- Schrostfutz_ is now known as Schrostfutz16:07
--- Log closed Tue Jul 21 00:00:25 2015

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