| --- Log opened Mon Jun 15 00:00:35 2015 | ||
| GeneralStupid | olofk: we did a audio delay in hardware... I think i could do that in software and i could do the serial to parallel and parallel to serial stuff into hardware ... | 09:47 |
|---|---|---|
| GeneralStupid | olofk: first i want to do it all in hardware, but i hope that its not possible (because of the performance) | 09:50 |
| GeneralStupid | olofk: an easier way for adding ip slaves into an working fusesoc would be nice... | 09:51 |
| stekern | GeneralStupid: why wouldn't it be possible to do all in hw? | 13:22 |
| GeneralStupid | stekern: it is possible, we already did this. But i just want to show how many lines of code could be saved ... | 13:27 |
| GeneralStupid | stekern: i just want to show that mor1k is working good enough | 13:27 |
| GeneralStupid | stekern: i mean: you have an fpga, so i could implement everything in "hardware" it would be the fastest way. But then i could use mor1k and implement everything is software... i want to have the advantages of an software implementation with the power of the hardware implementation. So thats what i want to do | 14:41 |
| stekern | GeneralStupid: but if you have already done a pure hw implementation, surely there are some parts you could identify that would be more suitable in sw? if not, then there's not much point in changing the design | 18:25 |
| GeneralStupid | stekern: for example the initial configuration and the configuration by uart would be nice in SW | 18:28 |
| GeneralStupid | stekern: the delay itself? | 18:28 |
| GeneralStupid | i dont know... | 18:29 |
| latif | hi everyone...good nights... | 18:45 |
| latif | is there anyone who can suggest me a good reference about how to add my own rtl modules to orpsoc-v2 ?? | 18:46 |
| latif | for exm.. I want to learn how to add a simple counter module to the orpsoc-v2.. may be someone have a good tutorial or a usefull pdf or ... :) | 18:48 |
| stekern | GeneralStupid: yeah, that's kind of stuff doesn't make sense in hw (the conf by uart) | 19:01 |
| stekern | latif: orpsocv2 has been outdated by fusesoc/orpsoc-cores | 19:02 |
| GeneralStupid | stekern: what do you think about parallel to serial and vice versa - i would say these would make a lot sense in hardware... | 19:02 |
| stekern | latif: this is a workshop centrated around that, it's a bit dated now, but probably the best guide: http://opencores.org/or1k/ORCONF2013_Workshop_ORPSoC_On_DE0_Nano | 19:05 |
| latif | stekern: Yes I know it is outdated but v3 has problems with the toolchain. I couldn't use it by loading program from spiflash . That's why I use v2. If you have a working spiflash driver can u please send me? | 19:54 |
| latif | Besides I am open to use v3 if there is a tutorial about binding custom RTL to the OpenRISC SOC | 19:55 |
| stekern | basically what you need to have is a wishbone interface and then instantiate it in the top level file | 20:03 |
| latif | stekern: Yes. It shold be like that. But how?? :) Thats what I have been looking.. | 21:06 |
| --- Log closed Tue Jun 16 00:00:36 2015 | ||
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