| --- Log opened Tue Apr 28 00:00:26 2015 | ||
| stekern | got aware about this from the musl mailing list: http://www.landley.net/notes-2015.html#12-04-2015 | 04:16 |
|---|---|---|
| stekern | BSD licensed sh2 core | 04:18 |
| stekern | wasn't Jörn the gcc maintainer for sh2 btw? | 04:21 |
| dalias | unfortunately i don't think they have a good solution for atomics yet :/ | 04:59 |
| dalias | they want to do SMP so fake atomics like old arm and classic superh had won't work | 04:59 |
| dalias | but i'm going to try to get this fixed before it's too late like i did with or1k :-) | 05:00 |
| stekern | yeah, I saw that from the ml. and you're right, musl was the driving force behind actually getting proper atomics in or1k ;) | 05:06 |
| olofk | This Open Processor Foundation seem a little bit shady. Perhaps mostly since I haven't heard of it before | 06:05 |
| olofk | And I can't find RTL anywhere which is never a good sign | 06:05 |
| olofk | From About OPF: "We also plan to start a dialog with OpenRISC folks" | 06:07 |
| olofk | latif: Did you rebuild newlib with the changes to _open ? | 06:55 |
| olofk | Alright! Finallly released v1.0 of the Wishbone BFM | 08:39 |
| bandvig | olofk: Could you say a bit more words about it? I'm not very familiar with interconnects. Is it an kernel for SoC building? Which are differences with interconnect used today? And so on. | 08:45 |
| olofk | bandvig: A BFM (Bus Functional Model) is like an API to generate bus transactions. Main use is for test benches where you can generate a lot of transactions to ensure that the design works as intended | 09:06 |
| olofk | And the Wishbone bus was originally developed together with OpenRISC. It's a fairly standard bus architecture with support for burst transactions to use bandwidth more efficiently | 09:07 |
| olofk | Most high-end SoC designs nowadays uses one of the buses in the AMBA family (such as AXI4 or AHB) | 09:07 |
| olofk | They are more complex, but have some advantages over wishbone in that they can handle different clock domains more efficiently, can pass metadata such as transaction identifers and allows for reading and writing at the same time | 09:08 |
| olofk | Unfortunately the license for AXI4 is a bit muddy. Otherwise we might have had more reason to switch over to that in some cases | 09:09 |
| olofk | The Wishbone BFM have mostly been used to verify that our memory controllers work correctly, and we have found some corner-case bugs with it | 09:13 |
| bandvig | olofk: If undestand correctly, I can use WB-BFM, for example: (1) to check for WB-compatibility of a "my" module (master or slave) (if I designed WB-interface myself) | 10:37 |
| bandvig | (2) directly use a part of BFM source code to fast create WB-compatible “bridge” to internals of a “my” module | 10:37 |
| bandvig | Is it correct? | 10:38 |
| _franck__ | bandvig: (1) WB-BFM is master only (2) I didn't look into WB-BFM source code by I guess that most of it is non synthesizable | 11:34 |
| _franck__ | s/by/but | 11:34 |
| latif | olofk: I am now trying it on my system..I hope it works.. thank you so much for your interest.. it took 2 months of my time... I have never thought that such a possibilty unfortunately.. | 11:37 |
| olofk | bandvig, _franck__ : Yes. There is both a master and a slave part in wb_bfm. If you look at the source code for wb_bfm you can see that I'm building a wishbone memory from the slave model | 11:43 |
| olofk | And as _franck__ said it's not synthesizable, so you can't use it in your design. But I'm trying to split out useful functions that can be synthesised to make it easier to implement wishbone stuff | 11:44 |
| _franck__ | olofk: cool, I didn't know wb_bfm has slave cabability | 11:45 |
| bandvig | olofk: frank: As far as I understand now, the WB-BFM is a kind of test suit to check correctness of various WB-transactions (if any implemented) in "my" master/slave module by RTL simulation | 11:48 |
| bandvig | right? | 11:48 |
| _franck__ | bandvig: right. It's also kind of an API you can use to write your own tests when you want access wishbone | 11:58 |
| _franck__ | https://github.com/olofk/wb_bfm/blob/master/wb_bfm_transactor.v | 11:59 |
| _franck__ | ^ this typically test memory by doing all kinds of writes/read and compare results | 12:00 |
| _franck__ | it uses wb_bfm sub-components | 12:01 |
| olofk | Another example of the slave capabilities is here https://github.com/openrisc/orpsoc-cores/blob/master/cores/uart16550_model/uart16550_model.v | 12:06 |
| olofk | That one is pretty crappy though, so don't view it as a good example :) | 12:07 |
| maxpaln | hmmm, got disconnected - hopefully no one replied while I was away! | 13:01 |
| maxpaln | ok, realised I didn't back in some changes I had already made on another design. Foolish error! I suspect my diagnosys was correct and that the problem was caused by a bug in my memory controller (the usual - almost ubiquitous culprit!) | 13:08 |
| bandvig | olof: franck: Thank you. | 13:32 |
| bandvig | olofk: it is very valuable achievement, especially if taking into account that the two most boring thing (at least for me) are writing tests and manuals ^) | 13:32 |
| maxpaln | I agree on manuals - unfortunately I am also one of those engineers who gets frustrated when the manuals are no help. Its a kind of unvirtuous circle... | 14:10 |
| latif | hi all, does any one know how to find the board.h file for atlys IF I AM USING ORPSOCV3 ?? | 16:15 |
| stekern | hmm, what board.h? | 16:18 |
| latif | the board.h file is the file which contains the adress data of ports..for exm adress of GPIO.. | 16:19 |
| latif | maybe the board.h file is renamed with orpsocV3 , but even so I dont know what are the new names and where they are?? | 16:21 |
| stekern | but for what software do you need it? the board.h in orpsocv2 was only used within orpsocv2 | 16:35 |
| stekern | the address should that are currently used should be backwards compatible though | 16:40 |
| latif | stekern: let me do it easy to tell..I am trying to do this example.. http://www.rte.se/blog/blogg-modesty-corex/writing-application-program/2.5 | 16:41 |
| latif | stekern: I am trying to access the gpio modules by using orpsocv3.. so I need GPIO adresses for atlys..in orpsocv2 the board.h file exist...bbut what about for V3?? | 16:43 |
| stekern | latif: you can get the memory map from this: https://github.com/openrisc/orpsoc-cores/blob/master/systems/atlys/data/wb_intercon.conf | 16:54 |
| latif | stekern: thanks for your interest...but How can I use this like board.h file?? for example GPIO_BASE_0 is not defined here?? | 16:58 |
| stekern | hmm? https://github.com/openrisc/orpsoc-cores/blob/master/systems/atlys/data/wb_intercon.conf#L68 | 17:02 |
| latif | stekern: ok I got it..but how will I use it my c code?? that's the problem.. what should I say for GPIO_BASE_0 | 17:05 |
| stekern | #define GPIO_BASE_0 0x91000000 | 17:05 |
| latif | hmm..let me try it..thanks stekern.. | 17:09 |
| latif | stkern: Do you have an idea about times_r error with or1k-elf-gcc compiler?? | 17:14 |
| latif | when we use a clock() function...it gives an error like undefined reference to _times_r | 17:15 |
| latif | stekern: by the way thecompiler returns an error..it is like.. ledtest.c: In function ‘main’: ledtest.c:6:30: error: expected declaration specifiers or ‘...’ before ‘*’ token #define writeGPIO(addr,val) (*(unsigned char*) (addr) = (val)) ^ ledtest.c:16:4: note: in expansion of macro ‘writeGPIO’ writeGPIO(GPIO_0_BASE+0x3,0xff); ^ ledtest.c:5:21: error: expected expression before â | 17:20 |
| stekern | GPIO_BASE_0 != GPIO_0_BASE | 17:23 |
| latif | olofk: my system crashed 2 times while installing the updated toolchain..I hope I will be able to say you the result :) | 18:04 |
| latif | does anyone know how any tutorial or something about accessing gpio ports by using orpsocv3..or maybe an easy code which should just run on openrisc..how can I do it on real hardware?? | 18:14 |
| olofk | latif: GPIO should be mapped to 0x91000000 on all known OpenRISC systems | 20:26 |
| --- Log closed Wed Apr 29 00:00:27 2015 | ||
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