IRC logs for #openrisc Saturday, 2015-03-28

--- Log opened Sat Mar 28 00:00:41 2015
shentinoHey stekern02:31
shentinooh heehee02:42
shentinoDoes openrisc have linux support yet?>02:42
daliashave you tried ?02:44
daliasyou can play with it in the browser02:45
daliasit boots faster in the emulator in the browser than most bloatware-based distros boot on real metal... ;-)02:46
daliasrunning mplayer on it at the moment just for fun02:48
shentinohey dalias, I got a pretend spec for a CPU I'd like to see built, wanna see?02:54
daliaswell it's not very specific03:27
shentinoI'm not a good doc writer03:41
shentinowhat sort of specific are you looking for?03:41
shentinoMy main goal was to make the cpu spec simple03:48
shentinoboth from the pov of the system designer and the programmer/compiler writer03:48
shentinoI honestly think that modern cpus are god awful complex beasts03:48
daliaswell there are two separate aspects to what you seem to want to do: designing the ISA, and designing the hardware04:37
daliasyour design is mostly ISA but has some mix of hardware implementation-specific details (like cache levels) and it has nothing in the way of specifics04:37
daliasfor example your list of instructions doesn't say anything about their operands, encodings, or how they work04:38
shentinouh...haven't gotten that far yet04:40
shentinothis whole thing is green as hell and right now it's mostly just a wish list04:41
shentinoISA stands for instruction set arch, right?04:43
daliasthe major omission i see in the ISA is any way to perform atomic compare-and-swap (cas, aka cmpxchg)04:55
shentinoI'm guessing that's a critical feature and plain old xchg isn't good enough05:00
daliasbut see that's part of what i meant by non-specific too05:10
daliasjust saying 'xchg' doesn't mean it's an atomic load/store exchange05:10
daliasit could just be swapping two registers (and that's what i'd assume just by seeing it in the list)05:10
shentinoI assumed too much familiarity with x86\05:13
shentinothanks for catching this05:13
shentinoI'm highly tempted to turf out the x86 set and just erase anything that doesn't fit, lol05:46
shentinomaking up my mind where to put everything05:46
daliasbtw if you want to see a nice simple ISA design (imo nicer than openrisc, hope they don't mind :) RISC-V is neat05:48
daliasbut being a risc design, somewhat different than something x86-like you seem to be looking for05:48
shentinohmm, where is risc-v?05:49
shentinofound it05:55
shentinomy isp hijacked nxdomain, made it hard to find05:56
shentinook good riscv is LE06:05
shentinodalias:  Are there docs for RISC-V that show the system architecture?  Like how virtual memory/interrupt handling works?07:25
Me1234olofk: It boots if I disconnect everything in assignments.07:52
Me1234olofk: It also boots with no ETH assignments (in pinmap.tcl and top) and expansion board disconnected07:59
olofkMe1234: Not sure I understood you correctly. Does it boot when you have the board connected, but all pin assignments relevant to the board removed from the pinmap and top-level?11:55
olofkrelevant to the expansion board I mean11:55
-!- Netsplit *.net <-> *.split quits: Lutin21:30
-!- Netsplit over, joins: Lutin21:35
--- Log closed Sun Mar 29 00:00:42 2015

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