| --- Log opened Sat Mar 28 00:00:41 2015 | ||
| shentino | Hey stekern | 02:31 |
|---|---|---|
| shentino | oh heehee | 02:42 |
| shentino | Does openrisc have linux support yet?> | 02:42 |
| dalias | yes | 02:44 |
| dalias | have you tried jor1k.com ? | 02:44 |
| dalias | you can play with it in the browser | 02:45 |
| dalias | it boots faster in the emulator in the browser than most bloatware-based distros boot on real metal... ;-) | 02:46 |
| dalias | running mplayer on it at the moment just for fun | 02:48 |
| shentino | hey dalias, I got a pretend spec for a CPU I'd like to see built, wanna see? | 02:54 |
| dalias | sure | 02:55 |
| shentino | thoughts? | 03:03 |
| dalias | well it's not very specific | 03:27 |
| shentino | I'm not a good doc writer | 03:41 |
| shentino | what sort of specific are you looking for? | 03:41 |
| shentino | My main goal was to make the cpu spec simple | 03:48 |
| shentino | both from the pov of the system designer and the programmer/compiler writer | 03:48 |
| shentino | I honestly think that modern cpus are god awful complex beasts | 03:48 |
| dalias | well there are two separate aspects to what you seem to want to do: designing the ISA, and designing the hardware | 04:37 |
| dalias | your design is mostly ISA but has some mix of hardware implementation-specific details (like cache levels) and it has nothing in the way of specifics | 04:37 |
| dalias | for example your list of instructions doesn't say anything about their operands, encodings, or how they work | 04:38 |
| shentino | uh...haven't gotten that far yet | 04:40 |
| shentino | this whole thing is green as hell and right now it's mostly just a wish list | 04:41 |
| shentino | ISA stands for instruction set arch, right? | 04:43 |
| dalias | yes | 04:54 |
| dalias | the major omission i see in the ISA is any way to perform atomic compare-and-swap (cas, aka cmpxchg) | 04:55 |
| shentino | I'm guessing that's a critical feature and plain old xchg isn't good enough | 05:00 |
| dalias | yes | 05:09 |
| dalias | but see that's part of what i meant by non-specific too | 05:10 |
| dalias | just saying 'xchg' doesn't mean it's an atomic load/store exchange | 05:10 |
| dalias | it could just be swapping two registers (and that's what i'd assume just by seeing it in the list) | 05:10 |
| shentino | ...derp | 05:12 |
| shentino | I assumed too much familiarity with x86\ | 05:13 |
| shentino | thanks for catching this | 05:13 |
| dalias | np | 05:15 |
| shentino | I'm highly tempted to turf out the x86 set and just erase anything that doesn't fit, lol | 05:46 |
| shentino | making up my mind where to put everything | 05:46 |
| dalias | btw if you want to see a nice simple ISA design (imo nicer than openrisc, hope they don't mind :) RISC-V is neat | 05:48 |
| dalias | but being a risc design, somewhat different than something x86-like you seem to be looking for | 05:48 |
| shentino | hmm, where is risc-v? | 05:49 |
| shentino | found it | 05:55 |
| shentino | my isp hijacked nxdomain, made it hard to find | 05:56 |
| shentino | ok good riscv is LE | 06:05 |
| shentino | dalias: Are there docs for RISC-V that show the system architecture? Like how virtual memory/interrupt handling works? | 07:25 |
| Me1234 | olofk: It boots if I disconnect everything in assignments. | 07:52 |
| Me1234 | olofk: It also boots with no ETH assignments (in pinmap.tcl and top) and expansion board disconnected | 07:59 |
| olofk | Me1234: Not sure I understood you correctly. Does it boot when you have the board connected, but all pin assignments relevant to the board removed from the pinmap and top-level? | 11:55 |
| olofk | relevant to the expansion board I mean | 11:55 |
| Me1234 | olofk:yes | 13:06 |
| -!- Netsplit *.net <-> *.split quits: Lutin | 21:30 | |
| -!- Netsplit over, joins: Lutin | 21:35 | |
| --- Log closed Sun Mar 29 00:00:42 2015 | ||
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