IRC logs for #openrisc Friday, 2015-03-06

--- Log opened Fri Mar 06 00:00:09 2015
sheridpDoes anyone have any examples of constraining an IOBUF with a UCF file when the IOBUF is not declared in the top module?00:52
sheridpIf anyone is interested, I think I found out how02:09
sheridpHmm, unfortunately, it can be done with SAVE attribute on an OBUF, but for some reason not an IOBUF02:58
sheridpOK, finally got it, but it's pretty unintuitive.  The reason for doing this is if you want to have more modular blocks.  E.g.:  I have a gpio module that I want connected to wishbone bus.  It seems ridiculous to pass the pin inouts all the way through the hierarchy to reach the top module, and it makes everything above the gpio peripheral less reusable since it has to be modified.04:36
juliusbsheridp: what constraints were you putting on them?10:23
mithroso a while back when opencores went down I did a git mirror of subversion, someone gave me access to freecores on GitHub with the intention of my making that sync happen frequently - anyone know who that might have been?13:08
stekernmithro: I would assume blueCmd13:19
mithroso someone contacted me about it - he said "Since OpenCore seems to be defunct by now (no svn access anymore since a week), it's time to move to a different platform."13:34
mithroblueCmd: do you know if that's true?13:36
mithroblueCmd: i've been syncing down to my local repos once in a while - but had not yet gotten around to pushing to github bit13:37
blueCmdmithro: I know there are some stirr on the mailinglists about OpenCores recently14:10
blueCmdTBH i don't keep up14:10
mithroblueCmd: I'm not even on the mailing lists :P14:11
jeremybennettjuliusb: wallento: Just to let you know I've seen your emails, and it looks good.  Bit snowed under at the moment, so email backlogged14:12
juliusbjeremybennett: Good to hear, thanks.16:00
sheridpjuliusb:  You want to be able to put a LOC constraint on a net that is not in the top module (so you don't have drag everything through the hierarchy).  The problem is that Xilinx only synthesizes IOBUFs on top module ports, so you need to declare these yourself.  But there's a further catch in that the "unused" port of the submodule will be trimmed during synthesis, so you have to add a (* S = "TRUE" *) flag to the port to prevent it from be19:22
sheridping eliminated19:22
mor1kx[mor1kx] skristiansson pushed 1 new commit to master:
mor1kxmor1kx/master 88cccaf Andrey Bacherov: add fpu32 support...21:12
mor1kx[mor1kx] skristiansson closed pull request #27: fpu32 support. prepare to pull request (master...withfpu)
mor1kx[mor1kx] skristiansson pushed 2 new commits to master:
mor1kxmor1kx/master 44b5095 Olof Kindgren: Add option to clear RF in simulations...21:17
mor1kxmor1kx/master 8f83372 Stefan Kristiansson: Merge branch 'master' of git://
stekernI'm on a roll tonight, sweeping away items in the todo pipeline21:20
stekernI submmitted a pull request for the or1k lk port too21:21
stekernolofk: "ERROR: 'mor1kx-generic' or any of its dependencies requires 'uart16550-1.5', but this core was not found"21:25
stekernI just pulled the latest and greatest bugs from orpsoc-cores ;)21:25
stekernmust been a long time since I updated fusesoc though, I can't even find my git clone of it...21:28
stekernmaybe the trial period has expired and it deleted itself?21:28
--- Log closed Sat Mar 07 00:00:11 2015

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