IRC logs for #openrisc Friday, 2015-02-27

--- Log opened Fri Feb 27 00:00:59 2015
stekernolofk: even after this?
olofkYes, even after that. Also, I had to copy to /lib as some symlink pointed to that07:00
olofkstekern: What's that python script doing there btw?07:06
olofkAnd this is the binary
stekernolofk: "Also"? all libs are already in /lib/09:09
stekern"it works here"(tm)09:10
stekernand the python script is there because I just copied all *so*09:11
GeneralStupidfusesoc didnt work for me at the moment if i do more pathing at my local repo to get it work, is it possible to get git access? i would like to help a bit. propably it would be a good idea if fusesoc support multiple repos10:16
GeneralStupidpathing => patching10:17
n0bawk.g fusesoc10:19
n0bawk,g fusesoc10:19
poke53281olofk: Did you solve your shared libs problem?10:42
stekernGeneralStupid: just do a pull-request with your changes10:52
GeneralStupidi need to get more into git :-D11:08
GeneralStupidim more that svn guy - its fine for my projects ( max. 3 members )11:08
olofkGeneralStupid: FuseSoC supports multiple repos11:29
olofkJust add them to the cores_root variable in fusesoc.conf11:29
olofkWith spaces between them11:29
olofkLater entries override earlier ones11:29
olofkAnd you can specify --cores-root=/path/to/cores to add more paths at runtime as well11:30
GeneralStupidi meant into the core configuration so one core tries e.g. Svn and if not available git ...11:34
olofkpoke53281: No, but I haven't tried anything more11:36
olofkstekern: Are you sure libc is there? There is a *.so entry in .gitignore, so you might have missed it11:36
olofkstekern: And does "it works here" mean that the ethtool I sent you works for you?11:37
olofkGeneralStupid: Yes, I've considered that, but we have only had one location for the repos, and that has worked fine until now, so I have prioritized other things11:38
olofkAnd as stekern said, just clone the repo and submit a pull request or send patches11:39
olofkif you have stuff that should be fixed11:39
stekernolofk: .gitignore... ah!11:40
stekern...and yes, the ethtool works11:42
olofkCould it be something with some collect something thingie?11:42
olofkstekern: Can you make your libc available somehow, so I can try with that?11:43
stekernI'm commenting out the *.so entry in my .gitignore and committing the .so files right now11:43
olofkI did a shallow clone. Will that come back to haunt me now when I pull?11:45
stekernwhat is a shallow clone?11:47
olofkclone --depth=111:47
olofkBecause computer is small and slow. Linux repo is huge11:47
stekernah, not sure11:48
olofkWell, I'll notice11:48
olofkGeneralStupid: Are you still having problems with adv_debug_sys?11:48
GeneralStupidyes i think so, but iam in a train so ill try later again11:49
olofkYeah, that's probably a good idea. There's a bug in FuseSoC that prevents it from working on trains11:50
olofkBut since I'm mostly travelling by bus I haven't fixed that yet11:50
stekernwhy can't I push to github now?11:53
GeneralStupidthat bug is called " there is no mobile internet faster then edge " 311:55
stekernolofk: try to pull now12:04
olofkYes! That works12:08
olofkWhy doesn't git apply always work? Nothing happens when I'm trying to apply one of the patches12:25
olofkNo errors. Nothing12:25
olofkApplying it with patch instead gives me a lot of failures12:30
stekernwhat does the patch look like?12:31
olofkDoes anyone have a local copy of the i2c svn repo I can copy? Want to check if there were some issues with the git conversion12:31
olofkstekern: It's the first patch in the i2c core if you have orpsoc-cores around12:32
olofkMight be line-endings or something like that12:32
olofkI cloned the i2c freecores repo and trying to apply the patches against that12:32
stekernapply that with 'git am' instead12:42
olofkThat almost worked13:25
olofkOr maybe not at all. Looks like it fails on the first chunk13:26
olofkFuck it. I give up13:29
Me1234___To use opencores ethmac what kernel config options are required? I have now only opencores ethmac driver enabled.15:02
stekernMe1234___: if you use the or1ksim_defconfig it becomes enabled15:06
GeneralStupidok, now fusesoc tells he is fetching adv_debug_sys but nothing happens15:58
olofkMe1234___: In my case, I  had to enable support for my Micrel phy as well16:28
olofkAt least I think it didn't work otherwise16:28
olofkThen you need to enable the networking stack as well of course, but the ethoc driver should be enough for the hw16:29
olofkGeneralStupid: Hmm...16:32
olofkNothing in ~/.cache/fusesoc/adv_debug_sys?16:32
GeneralStupidonly an .svn directory16:34
GeneralStupidshould try to delete it i guess16:34
Me1234___olofk: I think that opencores SVN is down. But I am not sure about now.16:36
GeneralStupidMe1234___: yes it is, because of that we/i try to change some to the github repo16:37
GeneralStupidolofk: is it ok to completely remove the .cache dir? Then everything should be fetched again?16:37
Me1234___GeneralStupid: fusesoc cache is located in .cache/fusesoc16:38
GeneralStupidMe1234___: i was just to lazy to write the whole path...16:39
GeneralStupid--verbose does not give me anything new16:41
olofkGeneralStupid: Yes, you can remove .cache/fusesoc and it should fetch thigns again17:03
olofkGeneralStupid: Did you replace the provider section in adv_debug_sys? Otherwise it will just try to fetch from opencores again17:08
olofkAnd the svn server seems to work enough to create the directory which is all FuseSoC looks at and assumes everything is downloaded ok17:09
olofkThis turned out to be a great fire drill for FuseSoC. Error handling is apparently not very good :)17:10
GeneralStupidolofk: yes i replace this17:11
GeneralStupidolofk: i dont know... i deleted the cache dir and now it does anything ...17:13
GeneralStupidgive me a minute :)17:13
GeneralStupidok jtag_tap is not reachable17:14
GeneralStupidi try changing it to github17:14
olofkGeneralStupid: That will unfortunately not work either :(17:19
olofkBut you might get away without that if you only want to build (not simulate)17:20
olofkRemove it from the depends17:21
GeneralStupidok, but the ERROR: Cannot find rtl/verilog/adbg_wb_biu.v in :17:21
GeneralStupidis back, because it isnt there17:21
olofkYes, you need to prefix all file paths with Hardware/adv_dbg_if/17:22
olofkIn adv_debug_sys.core17:22
GeneralStupidI think i need to change in system/de1/de1.core17:24
olofkGeneralStupid: Yes, remove jtag_tap from depend in that file17:27
GeneralStupidok i did but then adv_debug_sys is not like it should be17:27
olofkDid you fix the file paths in adv_debug_sys?17:27
GeneralStupidcopy Hardware/adv_dbg_if/ into the directory?17:29
GeneralStupidohh nice17:29 not found, but that should be easy to fix :-D17:29
olofkGeneralStupid: Just add quartus' bin directory to your path17:32
GeneralStupidbut there is no :/17:33
olofkThere shouldn't be a quartus.sh17:33
olofkJust a quartus17:33
olofkDoes FuseSoC tell you it's looking for
olofkGood. One step further at least. Might still be some build errors17:34
GeneralStupidyes sir17:34
GeneralStupidhe is missing the oe1200 top17:35
olofkComment out `define OR1200_CPU from de1/rtl/verilog/include/orpsoc-defines.v17:36
GeneralStupidbut should that be automatically, because i removed the dependence?17:39
GeneralStupidok ok propably i need to change the pinout17:42
GeneralStupid... fitter17:43
GeneralStupidolofk:  thats good, right?
olofkGeneralStupid: Sehr gut18:12
GeneralStupidthats bad :( my DE2 is at my home and i visit my parents at this weekend :)18:13
olofkWell, there are other things you need to fix as well.18:13
olofkGrab the schematic and find out the pinout for all your peripherals. Clock, reset, UART and memory to begin with18:14
GeneralStupidyes, thats the kind of work i love most :)18:15
olofkYes, that's one of the most ugly parts of this18:15
olofkBut Terasic might have some template you can start from18:15
olofkWas it a de2 70 or de2 115 btw?18:16
GeneralStupidonly de218:16
olofkaha. They really should take a look at how they name those things. It's very confusing18:17
olofk_Doh. Managed to slip on the keyboard and kill the screen session18:19
olofk_Or wait...18:19
olofk_olofk: Get out18:20
olofk_It would be great if someone could send over a copy of the OpenCores i2c repo. I have managed to patch the other cores, but there's something funky with that one18:25
GeneralStupidyes it is ...18:26
olofk_Ha! I found one on another partition18:26
GeneralStupidWe had de2-115 boards during the semester... but they first distribute their old de2 boards :)18:26
GeneralStupidWe can keep it :)18:27
olofk_Damn. That one was empty too :(18:27
olofk_Cool. Looks like nice boards18:28
GeneralStupidits really nice for playing or for developing stuff...18:28
GeneralStupidLots of outputs :)18:28
GeneralStupidlots of inputs18:28
GeneralStupidbut quartus is slooow18:28
olofk_Well. I can agree with all three statements :)18:35
olofk_But it's a lot faster than what ISE was a few years ago. It took 8 hours on our beefy build server for one device I was working on18:36
olofk_That one also had 180 clock domains, which kind of forced me to learn to constrain things properly :)18:36
stekernolofk_: is the one in cache the svn copy or does that have patches applied?18:43
olofk_stekern: It's got the patches applied18:44
olofk_stekern: You got a copy?18:44
stekernI've got cash!18:44
stekernerr... s/cash/cache18:45
olofk_Are you trying to set up a cache for cash deal? :)18:45
olofk_Fantastic! Thanks18:46
stekernI also have an almost working two level and one level pagetable implementation in lk18:47
stekernslightly annoying that the or1k l1 page table sections are 16MB...18:48
olofk_What would be a more common value for that?18:48
stekern1MB perhaps18:48
olofk_Does that mean you will only get half a page on many of the low end FPGA boards?18:49
stekernif I disregard what the arch manual says and ignore hw refill, I can of course set it up however I'd like18:49
stekernI had 1MB sections in the beginning, and no l2 tables at all18:50
olofk_What the hell is really in the freecores clone of i2c? It doesn't at all look like the one you sent me18:51
olofk_blueCmd: Do you remember any funkiness in i2c when doing the svn to git conversion?18:52
olofkscreen is confusing19:11
olofkok, so I think the problem with i2c is that the copy on freecores is broken19:12
olofkA local SVN copy doesn't contain older revisions, right?19:17
stekernolofk: no, svn is completely handicapped without the remote server19:46
olofkGahh.. I'll kill myself if I have to patch many more cores. Damn you OpenCores SVN!20:29
rschmidlinstekern, do you know why most memory controllers of orpsoc-cores systems incorporate arbiters and offers at least separate instruction and data interfaces?20:45
GeneralStupidolofk: :(20:46
rschmidlinstekern, why not rely on the interconnect arbiter itself?20:47
stekernrschmidlin: because often the memory controller has a better idea how to arbiter the data towards the memory than the generic arbiter20:49
rschmidlinThanks stekern. I was recently trying to put up a testing system myself using only blockrams (wb_ram_b3.v) for a starter. It did work. Surprisingly, it does not work with the caches. Any ideas?20:54
stekernI'd probably need a better definition of 'not work' to have ideas ;)20:55
rschmidlinCertainly :).20:56
GeneralStupidolofk: do you have the repositories?20:56
rschmidlinI have started an assembler which invalidate all cache lines and enables both caches and then starts a "Hello World".20:57
stekernbut, one thing that is different when you use caches is that the accesses are bursts, when they are disabled all accesses are 'classic'20:57
rschmidlinIf I don't enable the caches, it runs through.20:57
stekernwhich was the wb_ram_b3.v?20:57
rschmidlinwb_ram_b3.v should actually support burst accesses20:58
rschmidlinUnfortunatelly, I couldn't find out much on simulation since it works there.20:58
rschmidlinWhen I run it on FPGA, the CPU gets an exception.20:59
stekernwhat FPGA?21:00
rschmidlinI don't have my notes here. But I remember that the data cache got me a buserror. The instruction cache a trap, if the debugger is not misleading me here.21:00
rschmidlinArtix 621:00
rschmidlinThe design is timing clean. Thus, I'm kind of clueless here.21:01
rschmidlinOlof pointed me to try out wb_ram.v instead which actually made the system work with the data cache (boggles).21:02
rschmidlinFrom the instruction cache I still got the trap instruction. I thought it might come from non-invalidadted cache lines. But the trap opcode is not zeroes and I believe the lines would be zeroed on FPGA, wouldn't they?21:03
rschmidlinThat's where I suspected the arbiters/wishbone interface.21:03
rschmidlin--report done--21:03
stekernyou could try to half rule out/in mor1kx by just supporting classic cycles at the block ram21:05
rschmidlinI see, I deny the burst accesses and see if it works, meaning the bursts are not working reliably.21:12
stekernmor1kx is a bit picky about that the slaves implement the bursting correctly, but it's weird that it works in simulation for you21:16
stekernI've had some sim/target discrepancy on blockrams with Xilinx targets though21:17
rschmidlinvery. But I will only be able to test it on monday now. I have it running at work.21:17
rschmidlinstekern, in case that's the problem. How could I make the slave behave 'properly'?21:18
rschmidlinMy development board at home is a spartan3a-dsp-kit. I've been facing problems synthesizing mor1kx with ISE. I have adapted quite many spots last weekend and ran finally into multiple signal drivers on the data output of the internal cache rams.21:20
GeneralStupidrschmidlin: what exactly are you trying?21:20
stekernmultiple signal drivers?21:23
GeneralStupidit sounds a lot like what i want to do21:25
olofkrschmidlin: Come to think of it, I have a vague memory that blueCmd had some problems with the bursting using wb_ram on a Xilinx device. I think he disabled the bursting code in wb_ram21:25
rschmidlinuntil that point I was basically rewriting sensitivity lists of combinatorial blocks (always @(*)) that included memory arrays. ISE didnt like that. I have to launch ISE to check that, maybe I can paste the result to you.21:26
rschmidlinolofk, good call, history is on my side.21:27
stekernthat must be spartan3 specific, I haven't seen problems like that with ISE on other devices21:28
stekernbut if you have some results I can look at, by all means, give them to me ;)21:33
stekernand if you're able to do some on-chip logs I can take a look at them too21:34
olofkGeneralStupid: I got something for you21:34
olofkTake this archive :
olofkextract it somewhere and add the path to your fusesoc.conf21:36
rschmidlinGeneralStupid, I am trying to implement a basic mor1kx system on my spartan3a-dsp-kit21:42
olofkGeneralStupid: To explain a bit, these files will override the ones in your default orpsoc-cores so that you won't have to make any changes there21:43
olofkGot to sleep now. Daughter got a fever and wakes up every 20 minutes, so I will have to be prepared to do the same :)21:44
rschmidlini hope she gets better soon olof21:47
rschmidlinpastie does not allow me to paste the whole xst log21:47
rschmidlinstekern, I have created a file in my google drive and shared it with you21:49
GeneralStupidolofk: me too, thank you. I could host it on my subversion - if you are interested in. Because it would be easier to change (with perl for example)21:55
GeneralStupidrschmidlin: ok. Me Too21:55
GeneralStupidrschmidlin: but it sounds like you want to implement a coprocessor (IP Slave)21:56
GeneralStupidbut ... i propably misunderstood, i need some more informations about the wishbone21:58
--- Log closed Sat Feb 28 00:00:00 2015

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