IRC logs for #openrisc Monday, 2014-11-17

--- Log opened Mon Nov 17 00:00:32 2014
poke53281Did someone read about the new VISC CPU architecture in the news? Looks very interesting.  But I am not sure if I understand it correctly.05:25
poke53281Does that mean that I have a n core machine and these n cores can either work on one thread or on n threads or something in between?05:26
LoneTechdon't know, but that sounds interesting.07:06
olofkpoke53281: Is VISC implemented in JS? :)08:01
olofkWow! DFI became Interconnect tech of the year at DesignCon 200709:12
olofkThere must be at least as many awards as there are people on the planet09:13
stekernolofk: we should have some awards too!09:56
stekernbest beard etc09:56
olofkstekern: I love the idea :)09:56
olofkstekern: I love the idea :)09:57
stekernI hear you09:57
stekernI hear you09:58
stekernat least currently, I'm a strong contender10:00
olofkYou need to save it for next time10:01
stekernit all depends on what the winner will get10:04
stekernone year license of fusesoc ultimate and I'm in10:05
olofkI'll talk to the sales department and see what they can do10:09
olofkoh great. So opencores bugzilla is down12:51
olofkah no. My bad12:51
maxpalnolofk: lost a whole week to random stuff last week. About to pick up the the changes we discussed last week - just wanted to check I hadn't missed anything before I dived in13:12
maxpalnolofk: I have implemented the latest changes. I think this is everything now - I have added a new array called user_data[] that can be used instead of $random data for the write transactions - this is controlled via a top level parameter called USER_WRITE_DATA (set to any non-zero value). I have also updated the main transactor loop to mimic the original functionality when subtransactions=0,16:26
maxpalnthe final thing I did was clean up the wait state insertion - it's all handled inside wb_bfm_master now, much neater. If you want to try it out it is here ( I'll be back around later in the week in case you run into any problems.16:26
poke53281olofk: Don't know. Maybe in asm.js Otherwise they wouldn't get that speed. :)17:18
poke53281But I like to see finally a processor design, which might bring something new.17:19
poke53281I was a little bit disappointed about the 32->64 Bit transition the last decade. No new ideas. More registers, cleaned up instruction set.17:22
poke53281The only new design, which was a little bit more successful was the Itanium. And this CPU had a really interesting interface. The combination of three instructions in a group for example.17:24
poke53281Unfortunately VISC doesn't seem to be that different on the instruction set level. Everything interesting happens in the first few stages in the pipline.17:27
poke53281On a certain abstraction level I I find it really amazing how similar all those architectures are.17:33
poke53281olofk: I want to tell you this. I really like how simple OpenRISC is. It is clean and there are almost no strange side effects. It has much less flaws than the ARM 32 design for example. (Sum up the words "UNPREDICTABLE" and "UNDEFINED" in the ARM architecture manual . I guess there are a few hundreds. )17:41
stekernpoke53281: you forget "the mill"17:41
poke53281stekern: Never heard about it.17:44
poke53281Are there any chips build?17:47
poke53281At least on the paper it sound interesting.17:47
stekernafaik, there aren't really any implementations17:47
nmz787_ihi, anyone in here using Cadence tools (Concept Design Entry)?20:28
nmz787_iI see some mention of it in the logs20:28
nmz787_iI am working on scripting for schematics entry, and couldn't find a better search result than here or the Cadence forums20:29
--- Log closed Tue Nov 18 00:00:33 2014

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