IRC logs for #openrisc Wednesday, 2014-11-12

--- Log opened Wed Nov 12 00:00:24 2014
mor1kx[mor1kx] skristiansson pushed 1 new commit to master: https://github.com/openrisc/mor1kx/commit/e1b39475bed1899fefffc3eebf1426d730d8c9c806:05
mor1kxmor1kx/master e1b3947 Stefan Kristiansson: cappuccino/lsu: properly handle async reset for atomic_reserve...06:05
mor1kx[mor1kx] andrewray opened pull request #21: fix part selects for check_way_tag in d/icaches (master...way-tag-size) https://github.com/openrisc/mor1kx/pull/2111:49
olofkOh ffs. Winbond only supplies encrypted verilog models for their memories12:45
* olofk is not looking forward to blind testing DDR2 memories on a target board12:51
olofkstekern: I just read the orpsoc-cores issue regarding the rom size. Maybe we should move the base address down to 0xf0000000 instead. Any reasons against that?13:34
stekernnot really13:35
stekernbut it will not solve the issue13:35
mor1kx[mor1kx] skristiansson pushed 1 new commit to master: https://github.com/openrisc/mor1kx/commit/3b8e97241287ed594f589ae3bcce5428be19aa3d13:36
mor1kxmor1kx/master 3b8e972 andrewray: fix part selects for check_way_tag in d/icaches13:36
olofkstekern: No, that won't solve the issue, but it will allow us to have bootloaders > 256 bytes (or is it words?)14:39
olofkRight now we're limited to 0xf0000100-0xf00001ff14:40
olofkSure, the intercon could be made smarter, but that would also cost a lot more logic14:41
stekernah, right, now I understand your point15:10
-!- tariq786_lab is now known as tariq78617:14
--- Log closed Thu Nov 13 00:00:26 2014

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